NSK70721PE.C2 Intel, NSK70721PE.C2 Datasheet - Page 19

• Manufacturer Part Number: NSK70721PE.C2
• Manufacturer: Intel

Specifications of NSK70721PE.C2

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 28
• Lead Free Status / RoHS Status: Supplier Unconfirmed

3.1.2.1
3.1.3
Datasheet
Table 2
specifications.
Scrambling
The transmitted 2B1Q symbol must change value frequently to maintain appropriate power
spectral density, to limit low frequency content of the transmitted signal and to ensure that adequate
signal transitions are available for the receiver to recover clock phase information from the
received signal. A standardized mechanism has been adopted to ensure that adequate symbol
changes take place. This process is called scrambling, and generates a unique, self-synchronizing
pseudorandom data stream. The EMDP includes a data scrambler which complies with industry
standard scrambling and unscrambling rules. A 23rd-order polynomial is used to scramble and
descramble the data. The scrambler and descrambler polynomial used in the direction of Master to
Slave is X
Master is X
scrambler and descrambler refer to the following standards:
In some applications it may be necessary to bypass the scrambler. An example would be a framing
protocol which requires transmission of symbols with alternating +3 and -3 amplitudes. Direct
access to the 2B1Q encoder/decoder or the 2B1Q pulse generator is provided in some EMDP
operating modes (as described in subsequent sections) in which both bit clocks and quat clocks are
provided. Aligning the input data with both these clocks allows the desired quat to be transmitted.
When using these operating modes, the user application must ensure that the symbols transmitted
have been scrambled in a manner equivalent to that specified in the reference documents.
EDSP/IAFE Interface
TSGN, TMAG, and TX_CLK provide data interface from EDSP to IAFE. VCO_CLK, AD0 and
AD1 provide data interface from IAFE to EDSP. SER_CTL, SRCTL_FS, and AGC_SET provide
serial control interface between IAFE and EDSP.
Transmit data, represented by TSGN and TMAG, is clocked from the EDSP using the falling edge
of TX_CLK, the transmit clock. The IAFE uses the rising edge of TX_CLK to sample TSGN and
TMAG. TX_CLK is eight times the baud rate (equal to 4xBIT_CLK. e.g. for line rate of 784 kbps,
TX_CLK is 3.136 MHz). TSGN and TMAG change state at the baud rate, or every 8 cycles of
TX_CLK.
The IAFE provides the VCO_CLK to the EDSP which is generated by the IAFE’s internal VCO.
The A/D converter provides AD0 and AD1 outputs and coincides with the rising edge of
VCO_CLK/2. IAFE and EDSP both generate an internal VCO_CLK/2 from the same VCO_CLK.
The EDSP samples AD0 and AD1 with the falling edge of its internal VCO_CLK/2.
The serial control stream SER_CTL is provided by EDSP at the rate of VCO_CLK/2 and coincides
with its falling edge. A serial control frame strobe signal is also provided by the EDSP with its edge
transition occurring at every 16th of the VCO_CLK/2 period and coincides with the falling edge of
the VCO_CLK/2. The serial control stream SER_CTL and the framing signal SRCTL_FS is
sampled inside the IAFE at the rising edge of VCO_CLK/2.
Figure 5
•
•
•
ANSI Committee T1E1.4-TR28 (T1E1.4/96-006)
ETSI ETR-152
ITU G.991.1
lists the EDSP pin descriptions. Refer to Test Specifications for EDSP electrical and timing
shows relative timing for the EDSP/IAFE interface.
-23
-23
+X
+X
-5
-18
+1. The scrambler and descrambler polynomial used in the direction of Slave to
Enhanced Multi-Rate DSL Data Pump Chip Set — SK70725/SK70721
+1. Here ‘+’ symbol represents ‘Exclusive OR’ operation. For further details of
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