CYV15G0201DXB-BBI Cypress Semiconductor Corp, CYV15G0201DXB-BBI Datasheet
CYV15G0201DXB-BBI
Specifications of CYV15G0201DXB-BBI
Related parts for CYV15G0201DXB-BBI
CYV15G0201DXB-BBI Summary of contents
Page 1
... Note: 1. CYV15G0201DXB refers to SMPTE 259M and SMPTE 292M compliant devices. CYW15G0201DXB refers to OBSAI RP3 compliant devices (maximum operating data rate is 1540 MBaud). CYP15G0201DXB refers to devices not compliant to SMPTE 259M and SMPTE 292M pathological test requirements and also OBSAI RP3 operating datarate of 1536 MBaud. CYP(V)(W)15G0201DXB refers to all three devices. ...
Page 2
... The CYV15G0201DXB is verified by testing to be compliant to all the pathological test patterns, documented in SMPTE EG34-1999 for both the SMPTE 259M and 292M signaling rates. The tests ensure that the receiver recovers data with no errors for the following patterns: 1 ...
Page 3
... Transceiver Logic Block Diagram x10 Phase Align Buffer Encoder 8B/10B Serializer TX Document #: 38-02058 Rev. *H x10 x11 x11 Phase Elasticity Elasticity Align Buffer Buffer Buffer Decoder Encoder Decoder 8B/10B 8B/10B 8B/10B Framer Framer Deserializer Serializer Deserializer CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Page [+] Feedback ...
Page 4
... GND TXDA[4] TXCLKA GND GND NC TXDA[3] TXOPA GND GND SCSEL TXDA[2] TXPERA GND GND TXRST TXDA[ REFCLK- TXCLKO+ TXDA[ REFCLK+ TXCLKO CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB OUTB2– V INB1+ OUTB1– OUTB2+ V INB1– OUTB1+ BOE[3] CC PARCTL RFMODE V SDASEL BOE[2] CC TDI INSELB INSELA V ...
Page 5
... GND GND GND GND GND GND RXDA[2] RXDA[1] RXDA[0] NC GND GND TXCLKA TXDA[4] RXDA[6] RXDA[5] RXDA[4] RXDA[3] GND GND TXOPA TXDA[3] TXRST GND GND TXPERA TXDA[ TXDA[ TXDA[ CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB OUTA2– INA2 OUTA2+ INA2– TDO CC B LPEN V RFEN ...
Page 6
... TXCLKx and after allowing enough time for the TXPLL to lock to the reference clock (as specified by parameter t Note: 3. When REFCLK is configured for half-rate operation (TXRATE = HIGH), these inputs are sampled (or the outputs change) relative to both the rising and falling edges of REFCLK. Document #: 38-02058 Rev. *H CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Signal Description ). TXLOCK Page [+] Feedback ...
Page 7
... The LOW level is usually implemented by direct connection to V not connected or allowed to float, a 3-Level select input will self-bias to the MID level. Document #: 38-02058 Rev. *H Signal Description (ground). The HIGH level is usually implemented by direct connection CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB [3] . When MID, TXCLKx↑ is used (power). When CC Page ...
Page 8
... RXCLKA± outputs the recovered clock from either receive channel A or receive channel B as selected by RXCLKB+. These output clocks may operate at the character-rate or half the character-rate as selected by RXRATE. Document #: 38-02058 Rev. *H CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Signal Description th the serial symbol-rate) or character rate (1/10 ...
Page 9
... TXCTx[1:0] inputs are checked (along with TXOPx) for valid ODD parity, and ODD parity is generated for the RXDx[7:0] and RXSTx[2:0] outputs and presented on RXOPx. Document #: 38-02058 Rev. *H Signal Description MID, and the Encoder/Decoder CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB (TXMODE[1] ≠ LOW, are enabled Page [+] Feedback ...
Page 10
... Clock and Data Recovery internal pull-down (CDR) circuit. All serial drivers are forced to differential logic “1”. All serial data inputs are ignored. Document #: 38-02058 Rev. *H CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Signal Description Page [+] Feedback ...
Page 11
... Test Data Out. JTAG data output buffer which is High-Z while JTAG test mode is not LVTTL Output selected. TDI LVTTL Input, Test Data In. JTAG data input port. internal pull-up Power V +3.3V power. CC GND Signal and Power Ground for all internal circuits. Document #: 38-02058 Rev. *H CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Signal Description Page [+] Feedback ...
Page 12
... Word Sync Sequences TXDx[3] (TXMODE[1] = MID) and a Phase-Align Buffer error is present, the transmission of a Word Sync Sequence will TXDx[4] recenter the Phase Align Buffer and clear the error condition. TXDx[5] TXDx[6] TXDx[7] TXCTx[0] TXCTx[1] SCSEL CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB on both edges of REFCLK [6] Page [+] Feedback ...
Page 13
... IEEE standards for 8B/10B coded serial data streams. Transmit Modes The operating mode of the transmit path is set through the TXMODE[1:0] inputs. These 3-level select inputs allow one of nine transmit modes to be selected. The transmit modes are listed in Table 3. CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB ® ® ® ESCON and FICON ...
Page 14
... Once it has been successfully started, it cannot be stopped until all 16 characters have been generated. The content of the associated Input Register(s) is ignored for the duration of this 16-character sequence. CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Characters Generated or Page [+] Feedback ...
Page 15
... When operated in any configuration where receive channels are bonded together, TXCKSEL must be either LOW or HIGH (not MID) to ensure that associated characters are transmitted in the same character cycle. Document #: 38-02058 Rev. *H CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB TXCLKA↑. When the character accepted in the Channel-A Input Register has passed any selected validation and is ready to be passed to the Encoder, the level captured on SCSEL is passed to the Encoder of Channel-B during this same cycle ...
Page 16
... Serial Drivers may not meet all timing specifi- cations for up to 200 µs. Transmit PLL Clock Multiplier The Transmit PLL Clock Multiplier accepts a character-rate or half-character-rate external clock at the REFCLK input, and multiples that clock (as selected by TXRATE) to CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB BIST Receive PLL Output Channel Channel ...
Page 17
... LFIx output for each channel reports only the receive VCO frequency out-of-range and transition density status of the associated transmit signal. When local loopback is active, the Analog Signal Detect Monitors are disabled. CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB > 100 mV, or 200 mV peak-to-peak DIFF [11] Typical signal with peak amplitudes above ...
Page 18
... When a disabled receive channel is reenabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be indeterminate for ms. Document #: 38-02058 Rev. *H CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB of a bonded-pair is disabled, the other receive channels may not bind correctly. If the disabled channel is selected as the master channel for insert/delete functions, or recovered clock select, these functions will not work correctly ...
Page 19
... Table 24 and Table 25. Received Special Code characters are decoded using the Cypress column of Table 25. When DECMODE = HIGH, the 10-bit transmission characters are decoded using Table 24 and Table 25. Received Special Code characters are decoded using the Alternate column of Table 25. CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Page [+] Feedback ...
Page 20
... Independent Channel Modes In independent channel modes (RX Modes 0 and 1, where RXMODE[1] = LOW), both receive paths may be clocked in any clock mode selected by RXCKSEL. When RXCKSEL = LOW, both channels are clocked by REFCLK. RXCLKB± output is disabled (High-Z), and the CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Page [+] Feedback ...
Page 21
... Any disabled receive channel will indicate a constant LFIx output. When a disable receive channel is re-enabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be indeterminate for ms. CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Clock Source RXCLKA± RXCLKA RXCLKB ...
Page 22
... RXDx[7:0] character RXDx[7] • the RXDx[7:0] character and RXSTx[2:0] status. When the Decoders are bypassed (DECMODE = LOW), parity can be generated on • the RXDx[7:0] and RXSTx[1:0] bits • the RXDx[7:0] and RXSTx[2:0] bits. CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Bus Weight 10B Name COMDETx ...
Page 23
... Receive Synchronization State Machine, and are listed Table 18. The receive status when the channels are operated X X independently with channel bonding disabled is shown in Table 19. The receive status when Receive BIST is enabled shown in Table 20. CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB MID DECMODE DECMODE [17] ≠ LOW = LOW HIGH ...
Page 24
... When the channels are operated independently (with the Decoder enabled), this indicates a PLL Out of Lock condition. Also used to indicate receive Elasticity Buffer underflow/ overflow errors. CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Type-B Status Page [+] Feedback ...
Page 25
... Buffer Under/Overrun) OR (RX PLL Loss of Lock) OR (Four Consecutive Decoder Errors) OR (Invalid Minus Valid = 4) 6 Valid Character other than a FRAMCHAR Figure 2. Status Type-A Receive State Machine Document #: 38-02058 Rev RXSTx=101 RXSTx=111 State Transition Conditions CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Reset NO_SYNC 4 RESYNC 2 Page [+] Feedback ...
Page 26
... Last FRAMCHAR Before a Valid Character AND Bonded 7 (Elasticity Buffer Under/Overrun) OR (RX PLL Loss of Lock) Figure 3. Status Type-B Receive State Machine Document #: 38-02058 Rev. *H RXSTx = 101 5 RXSTx = 010 6 7 RXSTx = 101 Condition CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Reset NO_SYNC 4 3 RESYNC RXSTx=111 2 Page [+] Feedback ...
Page 27
... BIST Error. While comparing characters, a mismatch was found in one or more of the decoded character bits. 111 3 BIST Wait. The receiver is comparing characters. but has not yet found the start of BIST character to enable the LFSR. Document #: 38-02058 Rev. *H Type-A Status INVALID Receive BIST Status (Receive BIST = Enabled) CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Type-B Status Page [+] Feedback ...
Page 28
... Yes, RXSTx = Compare Next Character BIST_COMMAND_COMPARE (001) Match Command Data or Command Data End-of-BIST No State Yes, RXSTx = BIST_LAST_GOOD (010) No, RXSTx = BIST_ERROR (110) Figure 4. Receive BIST State Machine CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Receive BIST Detected LOW RX PLL Out of Lock RXSTx = RXSTx = BIST_DATA_COMPARE (000) Page [+] Feedback ...
Page 29
... 0.0V IN Min. ≤ V ≤ Max. CC Min. ≤ V ≤ Max. CC Min. ≤ V ≤ Max GND IN 100Ω differential load 150Ω differential load CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB V CC +3.3V ±5% +3.3V ±5% Min. Max. Unit 2 0.4 V –20 –100 mA –20 20 µ –0.5 0 ...
Page 30
... V ILE ≤ 270 ps ≤ [27] (d) CML/LVPECL Input Test Waveform requirement still needs to be satisfied. DIFFS = 3.3V 25°C, RXCKSEL = LOW, with all TX and RX channels enabled and one Serial CC A CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Min. Max. Unit V – 1.4 V – 0 – 1.4 V – 0.7 ...
Page 31
... The duty cycle specification is a simultaneous condition with the t cannot be as large as 30%–70%. Document #: 38-02058 Rev. *H Over the Operating Range Description and t parameters. This means that at faster character rates the REFCLK duty cycle REFH REFL CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Min. Max. Unit [28] 19.5 150 MHz [29] 6 ...
Page 32
... Hence: Total Jitter ( 14 20) (when RXRATE HIGH) or 1/(f * 10) (when RXRATE REF = LOW) of the remote transmitter if data is being received operating link this is equivalent to t CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Min. Max. Unit 9.5 ns 2.5 ns 10UI – 4.7 ns 0.5 ns 10UI – 4.3 ns –0.2 ns – ...
Page 33
... The TXCLKO output remains at the character rate regardless of the state of TXRATE and does not follow the duty cycle of REFCLK. Document #: 38-02058 Rev TXCLK t TXCLKH TXCLKL t TXDS t REFCLK t REFL t TREFDS t TREFDH t REFCLK t REFH Note 42 t TREFDS t REFCLK t REFH t TXCLKO t TXCLKOD- Note 43 CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB t TXDH t REFL t t TREFDS TREFDH t REFL Page [+] Feedback ...
Page 34
... Document #: 38-02058 Rev REFCLK t REFH REFL Note 44 t TXCLKO t TXCLKOD- t REFCLK t t REFH REFL t RREFDA t REFADV+ t REFCDV+ Note 45 t REFCLK t REFH t RREFDA t REFADV+ t REFCDV+ Note 45 CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB (continued) t RREFDV t REFADV- t REFCDV- t REFL t RREFDA t RREFDV t REFADV- t REFCDV- - Note 46 Page [+] Feedback ...
Page 35
... RXRATE = LOW RXCLKx+ RXCLKx– RXDx[7:0], RXSTx[2:0], RXOPx Receive Interface Read Timing RXCKSEL = HIGH or MID RXRATE = HIGH RXCLKx+ RXCLKx– RXDx[7:0], RXSTx[2:0], RXOPx Document #: 38-02058 Rev RXCLKP t RXCLKH RXCLKL t RXDV- t RXCLKP t RXCLKH t RXDV- CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB t RXDV+ t RXCLKL t RXDV+ Page [+] Feedback ...
Page 36
... RXOPB LVTTL 3-S OUT K11 RXCLKB+ LVTTL I/O PD K12 RXCLKB– LVTTL I/O PD K13 LFIB LVTTL OUT K14 TXCLKB LVTTL IN PD CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Ball ID Signal Name Signal Type E9 TXOPB LVTTL IN PU E10 TXPERB LVTTL OUT E11 TXCKSEL 3-LEVEL SEL E12 ...
Page 37
... LVTTL IN M3 VCC POWER M4 NC Not Connected M5 TXDA[2] LVTTL IN M6 TXPERA LVTTL OUT M7 GND GROUND M8 GND GROUND CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Ball ID Signal Name Signal Type N6 NC Not Connected N7 NC Not Connected N8 NC Not Connected N9 REFCLK– PECL IN N10 TXCLKO+ LVTTL OUT ...
Page 38
... HIGH). When c is set the decimal value of the binary number composed of the bits and A in that order, Document #: 38-02058 Rev. *H CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB and the y is the decimal value of the binary number composed of the bits H, G, and F in that order. When c is set and ...
Page 39
... Character in which the error occurred. Table 23 shows an example of this behavior. Character RD Character D21.1 – D10.2 101010 1001 – 010101 0101 101010 1011 + 010101 0101 D21.0 + D10.2 CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Data OUT 765 43210 Hex Value 000 00000 00 000 00001 01 000 00010 02 ...
Page 40
... D28.1 001 11100 010001 1011 D29.1 001 11101 100001 1011 D30.1 001 11110 010100 1011 D31.1 001 11111 CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 1001 011000 1001 011101 1001 100010 1001 101101 1001 010010 1001 110001 1001 ...
Page 41
... D28.3 011 11100 010001 0101 D29.3 011 11101 100001 0101 D30.3 011 11110 010100 0101 D31.3 011 11111 CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 0011 011000 1100 011101 0011 100010 1100 101101 0011 010010 1100 110001 1100 ...
Page 42
... D31.5 101 11111 011000 0110 D0.7 111 00000 100010 0110 D1.7 111 00001 010010 0110 D2.7 111 00010 CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Current RD− Current RD+ abcdei fghj abcdei fghj 100111 1010 011000 1010 011101 1010 100010 1010 101101 1010 010010 1010 110001 1010 ...
Page 43
... D28.7 111 11100 010001 0110 D29.7 111 11101 100001 0110 D30.7 111 11110 010100 0110 D31.7 111 11111 CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB Current RD− Current RD+ abcdei fghj abcdei fghj 110001 1110 110001 0001 110101 0001 001010 1110 101001 1110 101001 0001 011001 1110 ...
Page 44
... C1.7 (CE1) 111 00001 [58] C2.7 (CE2) 111 00010 [58] C4.7 (CE4) 111 00100 CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB [47, 48] Current RD− Current RD+ abcdei fghj abcdei fghj 001111 0100 110000 1011 001111 1001 110000 0110 001111 0101 110000 1010 001111 0011 110000 1100 ...
Page 45
... Ordering Information Speed Ordering Code Standard CYP15G0201DXB-BBC Standard CYP15G0201DXB-BBI Standard CYV15G0201DXB-BBC Standard CYV15G0201DXB-BBI OBSAI CYW15G0201DXB-BBC OBSAI CYW15G0201DXB-BBI Standard CYP15G0201DXB-BBXC Standard CYP15G0201DXB-BBXI Standard CYV15G0201DXB-BBXC Standard CYV15G0201DXB-BBXI OBSAI CYW15G0201DXB-BBXC OBSAI CYW15G0201DXB-BBXI Package Diagram 196-ball FBGA ( 1.5 mm) BB196A HOTLink is a registered trademark, and HOTLink II and MultiFrame are trademarks, of Cypress Semiconductor Corporation. ...
Page 46
... Added CYW15G0201DXB part number for OBSAI RP3 compliance to support operating data rate up to 1540 MBaud. Made changes to reflect OBSAI RP3 and CPR compliance. Added Pb-Free Package option for all parts listed in the datasheet. Changed MBd to MBaud in SPDSEL pin description CYP15G0201DXB CYV15G0201DXB CYW15G0201DXB min. values and t TREFDH REFCDV+ ...