CYV15G0201DXB-BBI Cypress Semiconductor Corp, CYV15G0201DXB-BBI Datasheet - Page 28
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CYV15G0201DXB-BBI
Manufacturer Part Number
CYV15G0201DXB-BBI
Description
Manufacturer
Cypress Semiconductor Corp
Datasheet
1.CYV15G0201DXB-BBI.pdf
(46 pages)
Specifications of CYV15G0201DXB-BBI
Lead Free Status / RoHS Status
Not Compliant
Document #: 38-02058 Rev. *H
JTAG Support
The CYP(V)(W)15G0201DXB contains a JTAG port to allow
system level diagnosis of device interconnect. Of the available
JTAG modes, only boundary scan is supported. This capability
is present only on the LVTTL inputs and outputs and the
REFCLK± clock input. The high-speed serial inputs and
outputs are not part of the JTAG test chain.
BIST_WAIT (111)
RXSTx =
BIST_DATA_COMPARE (000)/ BIST_COMMAND_COMPARE(001)
Yes
No
BIST_LAST_BAD (100)
Yes, RXSTx =
BIST Detected
End-of-BIST
Auto-Abort
Condition
Mismatch
Start of
State
BIST_START (101)
No
RXSTx =
BIST_ERROR (110)
Next Character
Yes, RXSTx =
No, RXSTx =
Figure 4. Receive BIST State Machine
Compare
Yes
BIST_LAST_GOOD (010)
No
Monitor Data
Buffer Error
Yes, RXSTx =
Received
Elasticity
End-of-BIST
Command
Data or
Match
State
Data
JTAG ID
The JTAG device ID for the CYP(V)(W)15G0201DXB is
‘1C80C069’x.
3-Level Select Inputs
Each 3-Level select input reports as two bits in the scan
register. These bits report the LOW, MID, and HIGH state of
the associated input as 00, 10, and 11, respectively.
BIST_COMMAND_COMPARE (001)
BIST_START (101)
Command
RXSTx =
No
RXSTx =
Detected LOW
Receive BIST
BIST_DATA_COMPARE (000)
CYW15G0201DXB
CYP15G0201DXB
CYV15G0201DXB
RXSTx =
Out of Lock
RX PLL
Page 28 of 46
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