HY82563EB S L7WG Intel, HY82563EB S L7WG Datasheet - Page 17

• Manufacturer Part Number: HY82563EB S L7WG
• Manufacturer: Intel

Specifications of HY82563EB S L7WG

• Lead Free Status / RoHS Status: Compliant

3.11
3.12
Table 10. Clock Generator Related Signals
Table 11. Power/Ground Pins (Sheet 1 of 2)
Clock Generator Interface
Power/Ground Pins
XTAL1
XTAL2
PHY_CLK_OUT
VSS
VSS
VDDO
Signal Name
Signal Name
82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
21
20
96
Pin
Central
Pad
89
11
22
60
75
97
Pin
I
A-o
O
Type
G
G
P
Type
TTL
A
TTL8
Sub-
Type
G
G
P
Sub-
Type
25 MHz Clock/Crystal Input
25 MHz +/- 50 ppm input. Can be connected to an oscillator or a
crystal. If using a crystal, XTAL2 must be connected as well. If a
crystal is used, it must be placed within ½-inch of the XTAL1 and
XTAL2 chip pins.
25 MHz Crystal Output
Output of internal oscillator circuit used to drive crystal into
oscillation. If using an oscillator, XTAL2 is left as a no connect.
Clock Output
Output clock available for use by a 631xESB/632xESB or other
component(s).
The speed depends on the how LINK_A is sampled at
LAN_PWR_GOOD assertion:
If LINK_A is 0b, the clock speed is 62.5 MHz.
If LINK_A is 1b, the clock speed is 25 MHz.
The output clock can be disabled depending on how LINK_B is
sampled at LAN_PWR_GOOD assertion:
If LINK_B is 0b: Clock output enabled (pulled-down).
If LINK_B is 1b: Clock output disabled (no connect).
Ground Exposed-Pad*
The ground is provided through a large central pad on the
bottom side of the package.
Ground
3.3V I/O Ring Power
Description
Description
11