HY82563EB S L7WG Intel, HY82563EB S L7WG Datasheet - Page 39

• Manufacturer Part Number: HY82563EB S L7WG
• Manufacturer: Intel

Specifications of HY82563EB S L7WG

• Lead Free Status / RoHS Status: Compliant

4.9
Table 33. Reset Specification
Power Consumption
There are no required timing relationships between PHY_RESET_N, PHY_SLEEP, and either
PHY_PWR_GOOD, the power supply being stable, or the oscillator being stable. The 82563EB/
82564EB will come out of reset when both PHY_PWR_GOOD is asserted (1b) and
PHY_RESET_N is deasserted (1b). It will be active when PHY_PWR_GOOD is asserted (1b),
PHY_RESET_N is deasserted (1b), and PHY_SLEEP is deasserted (0b).
The 82563EB/825654EB’s power consumption (Tables 34 through 37) is the sum of each port’s
power consumption. A port’s power consumption depends on whether the port’s logic, PHY, and
Kumeran are operational, and the 82563EB/825654EB’s operating speeds. These in turn, depend
on the following factors:
PHY_PWR_GOOD input
Kumeran Electrical Idle
PHY_PWR_GOOD pulse
Port Disable Register
PHY_RESET_N input
PHY_SLEEP input
PHY Power Down
Title
T
T
T
Power State
ppg
xoc
pco
Link Down
82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
Speed
Powers off the entire chip (including PHY_CLK_OUT) when 0b. It has priority
over PHY_RESET_N or PHY_SLEEP.
When 0b, the entire chip is held in reset except PHY_CLK_OUT.
When 1b the entire chip is powered down, except PHY_CLK_OUT.
The port’s PHY and Kumeran can be disabled by writing a 1b to the “Disable
Port” bit of the “Power Management Control” register.
ThE 82563EB/82564EB can be powered down with an indication over the
Kumeran bus or by writing a 1b to the “Control Register’s” “Power Down” bit.
When the link is required but the link is down the 82563EB/82564EB remains
in energy detect mode, attempting to detect energy from the link partner.
The 82563EB/82564EB uses progressively more power as the speed
increases from 10 Mb/s to 100 Mb/s to 1000 Mb/s. Speed is normally based on
auto-negotiation with the link partner, but may be forced or influenced by the
power state.
The power state can be used in conjunction with the “Low Power Link Up” and
“Auto-Negotiation 1000 Disable” to control the 82563EB/82564EB’s speed.
Nothing is transmitted on the differential pairs.
Minimum time PHY_PWR_GOOD must be
PHY_PWR_GOOD assertion, when using
Time from PHY_PWR_GOOD assertion
until the 82563EB/82564EB outputs the
low after power supply is in operating
Time from oscillator stable to
Minimum pulse width for
an external oscillator.
LAN_PWR_GOOD
PHY_CLK_OUT.
Description
range
Min
100
100
100
-
Max
350
-
-
-
Units
µs
µs
µs
µs
33