HY82563EB S L7WG Intel, HY82563EB S L7WG Datasheet - Page 26

• Manufacturer Part Number: HY82563EB S L7WG
• Manufacturer: Intel

Specifications of HY82563EB S L7WG

• Lead Free Status / RoHS Status: Compliant

82563EB/82564EB Gigabit Platform LAN Connect Networking Silicon
4.4.2
4.4.2.1
20
Table 20. 1.2V External Power Supply Parameters
a. The peak to peak output ripple is measured at 20 MHz Bandwidth within the operational range. The ripple must be included
Power Sequencing with External Regulators
The following power-on/off sequence should be applied when external power supplies are in use.
Designs must comply with the required power sequence to avoid risk of either latch-up or forward
biased internal diodes.
The general rule of thumb is that the 82563EB/82564EB power sequencing should power up the
three power rails in the following order: 3.3V
is not followed, there are specific requirements that must be adhered that are listed in the following
two sections.
External LVR Power up Sequencing and Tracking
Sequencing of the external supplies during power up may be necessary to ensure that the device is
not electrically overstressed and does not latch-up. These requirements are shown in
•
•
Overshoot Duration
Operational Range
within the operational range.
Capacitance ESR
The 82563EB/82564EB core voltage (1.2V) cannot exceed the 3.3V supply by more than 0.5V
at any time during the power up. The 82563EB/82564EB core voltage (1.2V) can not exceed
the 1.9V supply by more than 0.5V at any time during the power up. The core voltage is not
required to begin ramping before the 3.3V or the 1.9V supply.
The 82563EB/82564EB analog voltage (1.9V) cannot exceed the 3.3V supply by more than
0.5V at any time during the power up. The analog voltage is not required to begin ramping
before the 3.3V supply.
Monotonicity
Capacitance
Decoupling
Overshoot
Rise Time
Ripple
Slope
Title
Ramp rate at any given time between
Equivalent series resistance of output
(At that time delta voltage should be
Voltage range for normal operating
lower than 5 mV from steady state
Max: 0.8*V(max)/Rise time (min)
Maximum voltage ripple (peak to
Min: 0.8*V(min)/Rise time (max)
Time from 10% to 90% mark
Maximum overshoot allowed
Maximum overshoot allowed
Voltage dip allowed in ramp
Capacitance range
10% and 90%
Description
capacitance
conditions
duration.
voltage)
peak)
a
1.9V
1.2V. However, if this general guideline
1.08
Min
1.5
5
-
-
-
-
-
-
1500
Max
1.32
200
120
100
240
100
1
-
Figure
mV/ms
Units
M Ω
mV
mV
mV
ms
ms
µF
V
3.