XC95144XL-10TQG144I Xilinx Inc, XC95144XL-10TQG144I Datasheet

CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP

XC95144XL-10TQG144I

Manufacturer Part Number
XC95144XL-10TQG144I
Description
CPLD XC9500XL Family 3.2K Gates 144 Macro Cells 100MHz 0.35um (CMOS) Technology 3.3V 144-Pin TQFP
Manufacturer
Xilinx Inc
Series
XC9500XLr

Specifications of XC95144XL-10TQG144I

Package
144TQFP
Family Name
XC9500XL
Device System Gates
3200
Maximum Propagation Delay Time
10 ns
Number Of User I/os
117
Number Of Logic Blocks/elements
8
Typical Operating Supply Voltage
3.3 V
Maximum Operating Frequency
100 MHz
Number Of Product Terms Per Macro
90
Memory Type
Flash
Operating Temperature
-40 to 85 °C
Programmable Type
In System Programmable (min 10K program/erase cycles)
Delay Time Tpd(1) Max
10.0ns
Voltage Supply - Internal
3 V ~ 3.6 V
Number Of Logic Elements/blocks
8
Number Of Macrocells
144
Number Of Gates
3200
Number Of I /o
117
Mounting Type
Surface Mount
Package / Case
144-TQFP, 144-VQFP
Voltage
3.3V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Features
-
Number Of Logic Elements/cells
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
122-1375

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC95144XL-10TQG144I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC95144XL-10TQG144I
Manufacturer:
XILINX
0
Part Number:
XC95144XL-10TQG144I
Manufacturer:
Xilinx Inc.
Quantity:
4 482
k
DS054 (v2.5) May 22, 2009
Features
Table 1: XC9500XL Device Family
© 1998–2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other
countries. All other trademarks are the property of their respective owners.
DS054 (v2.5) May 22, 2009
Product Specification
Macrocells
Usable Gates
Registers
T
T
T
f
SYSTEM
PD
SU
CO
Optimized for high-performance 3.3V systems
-
-
-
-
-
-
-
Advanced system features
-
-
-
-
(ns)
(ns)
(ns)
5 ns pin-to-pin logic delays, with internal system
frequency up to 208 MHz
Small footprint packages including VQFPs, TQFPs
and CSPs (Chip Scale Package)
Pb-free available for all packages
Lower power operation
5V tolerant I/O pins accept 5V, 3.3V, and 2.5V
signals
3.3V or 2.5V output capability
Advanced 0.35 micron feature size CMOS
FastFLASH technology
In-system programmable
Superior pin-locking and routability with
FastCONNECT II switch matrix
Extra wide 54-input Function Blocks
Up to 90 product-terms per macrocell with
individual product-term allocation
(MHz)
R
XC9536XL
800
178
3.7
3.5
36
36
5
0
0
www.xilinx.com
0
XC9572XL
XC9500XL High-Performance CPLD
Family Data Sheet
Product Specification
1,600
178
3.7
3.5
72
72
5
-
-
-
-
-
-
Four pin-compatible device densities
-
Fast concurrent programming
Slew rate control on individual outputs
Enhanced data security features
Excellent quality and reliability
-
-
Pin-compatible with 5V core XC9500 family in common
package footprints
Local clock inversion with three global and one
product-term clocks
Individual output enable per output pin with local
inversion
Input hysteresis on all user and boundary-scan pin
inputs
Bus-hold circuitry on all user pin inputs
Supports hot-plugging capability
Full IEEE Std 1149.1 boundary-scan (JTAG)
support on all devices
36 to 288 macrocells, with 800 to 6400 usable
gates
10,000 program/erase cycles endurance rating
20 year data retention
XC95144XL
3,200
144
144
178
3.7
3.5
5
XC95288XL
6,400
288
288
208
4.0
3.8
6
1

XC95144XL-10TQG144I Summary of contents

Page 1

... Pin-compatible with 5V core XC9500 family in common package footprints XC9536XL XC9572XL 36 72 800 1,600 3.7 3.7 3.5 3.5 178 178 www.xilinx.com XC95144XL XC95288XL 144 288 3,200 6,400 144 288 5 6 3.7 4.0 3.5 3.8 178 208 1 ...

Page 2

... Notes: 1. The letter "G" as the third character indicates a Pb-free package. DS054 (v2.5) May 22, 2009 Product Specification XC9500XL High-Performance CPLD Family Data Sheet XC9536XL XC9572XL www.xilinx.com XC95144XL XC95288XL - - - - - - - - 117 - 117 117 117 117 117 - 168 168 - 192 192 - 192 192 - 192 192 2 ...

Page 3

R 3 JTAG Port I/O I/O I/O I/O I/O I/O I/O I/O 3 I/O/GCK 1 I/O/GSR I/O/GTS Note: Function block outputs (indicated by the bold lines) drive the I/O blocks directly. Family Overview The FastFLASH XC9500XL family ...

Page 4

R operation. The XC9500XL device exhibits symmetric full 3.3V output voltage swing to allow balanced rise and fall times. Additional details can be found in the application notes listed in "Further Reading" on page Architecture Description Each XC9500XL device is ...

Page 5

R 54 Product Allocator Figure 3: XC9500XL Macrocell Within Function Block All global control signals are available to each individual macrocell, including clock, set/reset, and output enable sig- nals. As shown in Figure 4, the macrocell register clock originates from ...

Page 6

R I/O/GSR I/O/GCK1 I/O/GCK2 I/O/GCK3 Figure 4: Macrocell Clock and Set/Reset Capability DS054 (v2.5) May 22, 2009 Product Specification XC9500XL High-Performance CPLD Family Data Sheet Product Term Set Product Term Clock Product Term Reset Global Set/Reset Global Clock 1 Global ...

Page 7

R Product Term Allocator The product term allocator controls how the five direct prod- uct terms are assigned to each macrocell. For example, all five direct terms can drive the OR function as shown in Figure 5. Product Term Allocator ...

Page 8

R The product term allocator can re-assign product terms from any macrocell within the FB by combining partial sums of products over several macrocells, as shown in In this example, the incremental delay is only 2 product terms are available ...

Page 9

R The internal logic of the product term allocator is shown in Figure 8. From Upper Macrocell From Lower Macrocell DS054 (v2.5) May 22, 2009 Product Specification XC9500XL High-Performance CPLD Family Data Sheet To Upper Macrocell Product Term Allocator To ...

Page 10

R FastCONNECT II Switch Matrix The FastCONNECT II Switch Matrix connects signals to the FB inputs, as shown in Figure 9. All IOB outputs (corre- FastCONNECT II Switch Matrix DS054 (v2.5) May 22, 2009 Product Specification XC9500XL High-Performance CPLD Family ...

Page 11

... Each input buffer provides input hysteresis CCIO (50 mV typical) to help reduce system noise for input signals ) to ensure that the with slow rise or fall edges. www.xilinx.com I/O Block Bus-Hold User- 1 Programmable Ground 0 Slew Rate Control Available in XC95144XL and XC95288XL DS054_10_042101 Figure 10 for I/O 11 ...

Page 12

R Each output driver is designed to provide fast switching with minimal power noise. All output drivers in the device may be configured for driving either 3.3V CMOS levels (which are compatible with 5V TTL levels as well) or 2.5V ...

Page 13

R The XC9500XL architecture provides for superior pin-lock- ing characteristics with a combination of large number of routing switches in the FastCONNECT II switch matrix, a 54-wide input Function Block, and flexible, bidirectional product term allocation within each macrocell. These ...

Page 14

R instructions are supported in each device. Additional instructions are included for in-system programming opera- tions. Design Security XC9500XL devices incorporate advanced data security fea- tures which fully protect the programming data against unauthorized reading or inadvertent device erasure/repro- gramming. ...

Page 15

R Detailed timing information may be derived from the full tim- ing model shown in Figure 16. The values and explanations Combinatorial Logic Propagation Delay = T (a) T PSU Combinatorial Logic P-Term Clock Path Setup Time = T PSU ...

Page 16

R Power-Up Characteristics During power-up, the XC9500XL device I/Os may be unde- fined until V rises above 1 Volt. This time period is CCINT called the subthreshold region, as transistors have not yet fully turned on powered ...

Page 17

R Further Reading Further information on the XC9500XL CPLD family can be found at: http://www.xilinx.com/support/documentation/xc9500xl.htm. This site includes: • Pinouts contained in the density-specific data sheets • Package electrical and thermal characteristics in UG112, Device Package User Guide • Termination, ...

Page 18

R Notice of Disclaimer THE XILINX HARDWARE FPGA AND CPLD DEVICES REFERRED TO HEREIN (“PRODUCTS”) ARE SUBJECT TO THE TERMS AND CONDITIONS OF http://www.xilinx.com/warranty.htm. THIS LIMITED WARRANTY DOES NOT EXTEND TO ANY USE OF PRODUCTS IN AN APPLICATION OR ENVIRONMENT ...

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