PIC16F1518-E/SP Microchip Technology, PIC16F1518-E/SP Datasheet - Page 201

• Manufacturer Part Number: PIC16F1518-E/SP
• Description: 28-pin, 28KB Flash, 1024B RAM, 10-bit ADC, 2xCCP, SPI, MI2C, EUSART, 2.3V-5.5V 2
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F1518-E/SP

• Processor Series: PIC16F151x
• Core: PIC
• Data Bus Width: 8 bit
• Program Memory Type: Flash
• Program Memory Size: 16 KB
• Data Ram Size: 1 KB
• Interface Type: I2C, SPI, USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 25
• Number Of Timers: 3
• Operating Supply Voltage: 2.3 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• Package / Case: PDIP-28
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 25
• Eeprom Size: -
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 5.5 V
• Data Converters: A/D 17x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Lead Free Status / Rohs Status: Details

21.5.2
When the R/W bit of a matching received address byte
is clear, the R/W bit of the SSPSTAT register is cleared.
The received address is loaded into the SSPBUF reg-
ister and Acknowledged.
When the overflow condition exists for a received
address, then not Acknowledge is given. An overflow
condition is defined as either bit BF bit of the SSPSTAT
register is set, or bit SSPOV bit of the SSPCON1 reg-
ister is set. The BOEN bit of the SSPCON3 register
modifies this operation. For more information see
Register
An MSSP interrupt is generated for each transferred
data byte. Flag bit, SSPIF, must be cleared by software.
When the SEN bit of the SSPCON2 register is set, SCL
will be held low (clock stretch) following each received
byte. The clock must be released by setting the CKP
bit of the SSPCON1 register, except sometimes in
10-bit mode. See
for more detail.
21.5.2.1
This section describes a standard sequence of events
for the MSSP module configured as an I
7-bit Addressing mode. All decisions made by hard-
ware or software and their effect on reception.
Figure 21-13
reference for this description.
This is a step by step process of what typically must
be done to accomplish I
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Software clears SSPIF.
11. Software reads the received byte from SSPBUF
12. Steps 8-12 are repeated for all received bytes
13. Master sends Stop condition, setting P bit of
 2011 Microchip Technology Inc.
Start bit detected.
S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
Matching address with R/W bit clear is received.
The slave pulls SDA low sending an ACK to the
master, and sets SSPIF bit.
Software clears the SSPIF bit.
Software reads received address from SSPBUF
clearing the BF flag.
If SEN = 1; Slave software sets CKP bit to
release the SCL line.
The master clocks out a data byte.
Slave drives SDA low sending an ACK to the
master, and sets SSPIF bit.
clearing BF.
from the master.
SSPSTAT, and the bus goes Idle.
21-4.
SLAVE RECEPTION
7-bit Addressing Reception
and
Section 21.2.3 “SPI Master Mode”
Figure 21-14
2
C communication.
is used as a visual
2
C Slave in
Preliminary
21.5.2.2
Slave device reception with AHEN and DHEN set
operate the same as without these options with extra
interrupts and clock stretching added after the 8th fall-
ing edge of SCL. These additional interrupts allow the
slave software to decide whether it wants to ACK the
receive address or data byte, rather than the hard-
ware. This functionality adds support for PMBus™ that
was not present on previous versions of this module.
This list describes the steps that need to be taken by
slave software to use these options for I
cation.
address and data holding.
operation with the SEN bit of the SSPCON2 register
set.
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Slave clears SSPIF.
11. SSPIF set and CKP cleared after 8th falling
12. Slave looks at ACKTIM bit of SSPCON3 to
13. Slave reads the received data from SSPBUF
14. Steps 7-14 are the same for each received data
15. Communication is ended by either the slave
Note: SSPIF is still set after the 9th falling edge of
PIC16(L)F1516/7/8/9
S bit of SSPSTAT is set; SSPIF is set if interrupt
on Start detect is enabled.
Matching address with R/W bit clear is clocked
in. SSPIF is set and CKP cleared after the 8th
falling edge of SCL.
Slave clears the SSPIF.
Slave can look at the ACKTIM bit of the
SSPCON3 register to determine if the SSPIF
was after or before the ACK.
Slave reads the address value from SSPBUF,
clearing the BF flag.
Slave sets ACK value clocked out to the master
by setting ACKDT.
Slave releases the clock by setting CKP.
SSPIF is set after an ACK, not after a NACK.
If SEN = 1 the slave hardware will stretch the
clock after the ACK.
edge of SCL for a received data byte.
determine the source of the interrupt.
clearing BF.
byte.
sending an ACK = 1, or the master sending a
Stop condition. If a Stop is sent and Interrupt on
Stop Detect is disabled, the slave will only know
by polling the P bit of the SSTSTAT register.
Figure 21-15
SCL even if there is no clock stretching and
BF has been cleared. Only if NACK is sent
to master is SSPIF not set
7-bit Reception with AHEN and DHEN
displays a module using both
Figure 21-16
DS41452B-page 201
2
includes the
C communi