PIC16F1937T-I/MV Microchip Technology, PIC16F1937T-I/MV Datasheet - Page 193
![14KB Flash, 512B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm T/R](/photos/16/12/161286/qfn44_sml.jpg)
PIC16F1937T-I/MV
Manufacturer Part Number
PIC16F1937T-I/MV
Description
14KB Flash, 512B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F1937-EMV.pdf
(472 pages)
Specifications of PIC16F1937T-I/MV
Processor Series
PIC16F
Core
PIC
Program Memory Type
Flash
Program Memory Size
14 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
UQFN-40
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
- Current page: 193 of 472
- Download datasheet (5Mb)
20.2
REGISTER 20-1:
TABLE 20-1:
2008-2011 Microchip Technology Inc.
CPSCON0
INTCON
OPTION_REG
TMR0
TRISA
Legend:
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2-0
R/W-1/1
WPUEN
Name
*
Option and Timer0 Control Register
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the Timer0 module.
Page provides register information.
Timer0 Module Register
WPUEN: Weak Pull-up Enable bit
1 = All weak pull-ups are disabled (except MCLR, if it is enabled)
0 = Weak pull-ups are enabled by individual WPUx latch values
INTEDG: Interrupt Edge Select bit
1 = Interrupt on rising edge of INT pin
0 = Interrupt on falling edge of INT pin
TMR0CS: Timer0 Clock Source Select bit
1 = Transition on T0CKI pin
0 = Internal instruction cycle clock (F
TMR0SE: Timer0 Source Edge Select bit
1 = Increment on high-to-low transition on T0CKI pin
0 = Increment on low-to-high transition on T0CKI pin
PSA: Prescaler Assignment bit
1 = Prescaler is not assigned to the Timer0 module
0 = Prescaler is assigned to the Timer0 module
PS<2:0>: Prescaler Rate Select bits
CPSON
WPUEN
TRISA7
SUMMARY OF REGISTERS ASSOCIATED WITH TIMER0
INTEDG
R/W-1/1
Bit 7
GIE
OPTION_REG: OPTION REGISTER
Bit Value
INTEDG
000
001
010
011
100
101
110
111
TRISA6
PEIE
Bit 6
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
—
TMR0CS
R/W-1/1
Timer0 Rate
TMR0CS
TMR0IE
TRISA5
1 : 2
1 : 4
1 : 8
1 : 16
1 : 32
1 : 64
1 : 128
1 : 256
Bit 5
—
TMR0SE
R/W-1/1
TMR0SE
TRISA4
INTE
Bit 4
OSC
—
/4)
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
R/W-1/1
TRISA3
PSA
IOCIE
Bit 3
PSA
CPSRNG<1:0>
PIC16(L)F1934/6/7
TMR0IF
TRISA2
Bit 2
R/W-1/1
PS<2:0>
CPSOUT
TRISA1
Bit 1
INTF
PS<2:0>
R/W-1/1
TRISA0
T0XCS
IOCIF
DS41364E-page 193
Bit 0
R/W-1/1
Register
on Page
191*
323
193
133
98
bit 0
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