PIC16F1937T-I/MV Microchip Technology, PIC16F1937T-I/MV Datasheet - Page 249
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PIC16F1937T-I/MV
Manufacturer Part Number
PIC16F1937T-I/MV
Description
14KB Flash, 512B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F1937-EMV.pdf
(472 pages)
Specifications of PIC16F1937T-I/MV
Processor Series
PIC16F
Core
PIC
Program Memory Type
Flash
Program Memory Size
14 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
UQFN-40
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
- Current page: 249 of 472
- Download datasheet (5Mb)
24.2.6
In SPI Master mode, module clocks may be operating
at a different speed than when in Full Power mode; in
the case of the Sleep mode, all clocks are halted.
Special care must be taken by the user when the MSSP
clock is much faster than the system clock.
In Slave mode, when MSSP interrupts are enabled,
after the master completes sending data, an MSSP
interrupt will wake the controller from Sleep.
If an exit from Sleep mode is not desired, MSSP
interrupts should be disabled.
TABLE 24-1:
2008-2011 Microchip Technology Inc.
ANSELA
APFCON
INTCON
PIE1
PIR1
SSPBUF
SSPCON1
SSPCON3
SSPSTAT
TRISA
TRISC
Legend:
Name
*
— = Unimplemented location, read as ‘0’. Shaded cells are not used by the MSSP in SPI mode.
Page provides register information.
SPI OPERATION IN SLEEP MODE
Synchronous Serial Port Receive Buffer/Transmit Register
TMR1GIE
TMR1GIF
ACKTIM
TRISA7
TRISC7
WCOL
Bit 7
SMP
GIE
—
—
SUMMARY OF REGISTERS ASSOCIATED WITH SPI OPERATION
CCP3SEL
TRISC6
SSPOV
TRISA6
ADIE
PCIE
Bit 6
PEIE
ADIF
CKE
—
T1GSEL
TMR0IE
TRISC5
SSPEN
TRISA5
ANSA5
RCIE
RCIF
SCIE
Bit 5
D/A
P2BSEL
TRISA4
TRISC4
ANSA4
BOEN
INTE
TXIE
Bit 4
TXIF
CKP
P
SRNQSEL
SSP1IE
SSP1IF
TRISA3
TRISC3
ANSA3
SDAHT
IOCIE
Bit 3
In SPI Master mode, when the Sleep mode is selected,
all module clocks are halted and the transmis-
sion/reception will remain in that state until the device
wakes. After the device returns to Run mode, the mod-
ule will resume transmitting and receiving data.
In SPI Slave mode, the SPI Transmit/Receive Shift
register operates asynchronously to the device. This
allows the device to be placed in Sleep mode and data
to be shifted into the SPI Transmit/Receive Shift
register. When all 8 bits have been received, the MSSP
interrupt flag bit will be set and if enabled, will wake the
device.
S
PIC16(L)F1934/6/7
C2OUTSEL
TMR0IF
CCP1IE
CCP1IF
SBCDE
TRISA2
TRISB2
ANSA2
Bit 2
R/W
SSPM<3:0>
TMR2IE
TMR2IF
TRISA1
TRISC1
ANSA1
SSSEL
AHEN
Bit 1
INTF
UA
CCP2SEL
TMR1IE
TMR1IF
TRISC0
TRISA0
ANSA0
DHEN
IOCIF
DS41364E-page 249
Bit 0
BF
Register
on Page
243*
134
131
102
287
289
286
133
142
98
99
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