PIC16F1937T-I/MV Microchip Technology, PIC16F1937T-I/MV Datasheet - Page 292
![14KB Flash, 512B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm T/R](/photos/16/12/161286/qfn44_sml.jpg)
PIC16F1937T-I/MV
Manufacturer Part Number
PIC16F1937T-I/MV
Description
14KB Flash, 512B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F1937-EMV.pdf
(472 pages)
Specifications of PIC16F1937T-I/MV
Processor Series
PIC16F
Core
PIC
Program Memory Type
Flash
Program Memory Size
14 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
UQFN-40
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
- Current page: 292 of 472
- Download datasheet (5Mb)
PIC16(L)F1934/6/7
FIGURE 25-2:
The operation of the EUSART module is controlled
through three registers:
• Transmit Status and Control (TXSTA)
• Receive Status and Control (RCSTA)
• Baud Rate Control (BAUDCON)
These
Register 25-2
When the receiver or transmitter section is not enabled
then the corresponding RX or TX pin may be used for
general purpose input and output.
DS41364E-page 292
BRG16
Baud Rate Generator
SPBRGH
registers
and
SPBRGL
Register
RX/DT pin
are
+ 1
EUSART RECEIVE BLOCK DIAGRAM
detailed
25-3, respectively.
Multiplier
BRG16
SYNC
BRGH
Pin Buffer
and Control
in
SPEN
1 X 0 0
X 1 1 0
X 1 0 1
x4
Register
x16 x64
F
OSC
0
0
0
25-1,
n
Data
Recovery
÷ n
FERR
Stop
MSb
CREN
(8)
RX9D
2008-2011 Microchip Technology Inc.
7
RX9
RSR Register
RCREG Register
• • •
OERR
8
1
RCIF
RCIE
Data Bus
0
START
LSb
RCIDL
Interrupt
FIFO
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