PIC16F1937T-I/MV Microchip Technology, PIC16F1937T-I/MV Datasheet - Page 289
![14KB Flash, 512B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm T/R](/photos/16/12/161286/qfn44_sml.jpg)
PIC16F1937T-I/MV
Manufacturer Part Number
PIC16F1937T-I/MV
Description
14KB Flash, 512B RAM, 256B EEPROM, LCD, 1.8-5.5V 40 UQFN 5x5x0.5mm T/R
Manufacturer
Microchip Technology
Series
PIC® XLP™ 16Fr
Datasheet
1.PIC16F1937-EMV.pdf
(472 pages)
Specifications of PIC16F1937T-I/MV
Processor Series
PIC16F
Core
PIC
Program Memory Type
Flash
Program Memory Size
14 KB
Data Ram Size
256 B
Interface Type
MI2C, SPI, EUSART
Number Of Timers
5
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Package / Case
UQFN-40
Development Tools By Supplier
MPLAB IDE Software
Minimum Operating Temperature
- 40 C
Core Processor
PIC
Core Size
8-Bit
Speed
32MHz
Connectivity
I²C, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
36
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 14x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Lead Free Status / Rohs Status
Details
- Current page: 289 of 472
- Download datasheet (5Mb)
REGISTER 24-4:
2008-2011 Microchip Technology Inc.
bit 7
Legend:
R = Readable bit
u = Bit is unchanged
‘1’ = Bit is set
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
ACKTIM
R-0/0
2:
3:
For daisy-chained SPI operation; allows the user to ignore all but the last received byte. SSPOV is still set
when a new byte is received and BF = 1, but hardware continues to write the most recent byte to SSPBUF.
This bit has no effect in Slave modes that Start and Stop condition detection is explicitly listed as enabled.
The ACKTIM Status bit is only active when the AHEN bit or DHEN bit is set.
ACKTIM: Acknowledge Time Status bit (I
1 = Indicates the I
0 = Not an Acknowledge sequence, cleared on 9
PCIE: Stop Condition Interrupt Enable bit (I
1 = Enable interrupt on detection of Stop condition
0 = Stop detection interrupts are disabled
SCIE: Start Condition Interrupt Enable bit (I
1 = Enable interrupt on detection of Start or Restart conditions
0 = Start detection interrupts are disabled
BOEN: Buffer Overwrite Enable bit
In SPI Slave mode:
In I
In I
SDAHT: SDA Hold Time Selection bit (I
1 = Minimum of 300 ns hold time on SDA after the falling edge of SCL
0 = Minimum of 100 ns hold time on SDA after the falling edge of SCL
SBCDE: Slave Mode Bus Collision Detect Enable bit (I
If on the rising edge of SCL, SDA is sampled low when the module is outputting a high state, the BCLIF
bit of the PIR2 register is set, and bus goes Idle
1 = Enable slave bus collision interrupts
0 = Slave bus collision interrupts are disabled
AHEN: Address Hold Enable bit (I
1 = Following the 8th falling edge of SCL for a matching received address byte; CKP bit of the
0 = Address holding is disabled
DHEN: Data Hold Enable bit (I
1 = Following the 8th falling edge of SCL for a received data byte; slave hardware clears the CKP bit
0 = Data holding is disabled
R/W-0/0
2
2
PCIE
C Master and SPI Master mode:
C Slave mode:
This bit is ignored.
1 = SSPBUF updates every time that a new data byte is shifted in ignoring the BF bit
0 = If new byte is received with BF bit of the SSPSTAT register already set, SSPOV bit of the
1 = SSPBUF is updated and ACK is generated for a received address/data byte, ignoring the state
0 = SSPBUF is only updated when SSPOV is clear
SSPCON1 register will be cleared and the SCL will be held low.
of the SSPCON1 register and SCL is held low.
SSPCON3: SSP CONTROL REGISTER 3
SSPCON1 register is set, and the buffer is not updated
of the SSPOV bit only if the BF bit = 0.
W = Writable bit
x = Bit is unknown
‘0’ = Bit is cleared
R/W-0/0
2
SCIE
C bus is in an Acknowledge sequence, set on 8
(1)
2
R/W-0/0
C Slave mode only)
BOEN
2
C Slave mode only)
2
C mode only)
2
(2)
(2)
C mode only)
2
U = Unimplemented bit, read as ‘0’
-n/n = Value at POR and BOR/Value at all other Resets
2
C mode only)
C mode only)
R/W-0/0
SDAHT
TH
rising edge of SCL clock
PIC16(L)F1934/6/7
2
(3)
C Slave mode only)
R/W-0/0
SBCDE
TH
falling edge of SCL clock
R/W-0/0
AHEN
DS41364E-page 289
R/W-0/0
DHEN
bit 0
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