PIC16F721T-I/ML Microchip Technology, PIC16F721T-I/ML Datasheet - Page 17

• Manufacturer Part Number: PIC16F721T-I/ML
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 QFN 4x4mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721T-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 2-1:
 2010 Microchip Technology Inc.
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend:
Note 1:
Address
Bank 0
(
(
(
(
(
(
2
2
2
2
1
2
)
)
)
)
),(
)
2:
3:
4:
5:
2
)
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
These registers can be addressed from any bank.
Accessible only when SSPM<3:0> = 1001.
This bit is unimplemented and reads as ‘1’.
See
INDF
TMR0
PCL
STATUS
FSR
PORTA
PORTB
PORTC
PCLATH
INTCON
PIR1
TMR1L
TMR1H
T1CON
TMR2
T2CON
SSPBUF
SSPCON
CCPR1L
CCPR1H
CCP1CON
RCSTA
TXREG
RCREG
ADRES
ADCON0
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Register
Name
—
—
—
—
—
—
SPECIAL FUNCTION REGISTER SUMMARY
6-2.
TMR1CS1
TMR1GIF
WCOL
SPEN
Bit 7
RB7
RC7
IRP
GIE
—
—
—
—
—
Addressing this location uses contents of FSR to address data memory (not a physical register)
TMR1CS0
TOUTPS3
Holding Register for the Least Significant Byte of the 16-bit TMR1 Register
Holding Register for the Most Significant Byte of the 16-bit TMR1 Register
SSPOV
Bit 6
PEIE
ADIF
RC6
RX9
RP1
RB6
—
—
—
—
Synchronous Serial Port Receive Buffer/Transmit Register
TOUTPS2
T1CKPS1
TMR0IE
SSPEN
Program Counter (PC) Least Significant Byte
SREN
CHS3
Capture/Compare/PWM Register High Byte
RCIF
Capture/Compare/PWM Register Low Byte
Bit 5
RC5
DC1
RP0
RA5
RB5
—
Indirect Data Memory Address Pointer
AUSART Transmit Data Register
AUSART Receive Data Register
Timer0 module Register
Timer2 module Register
ADC Result Register
TOUTPS1
T1CKPS0
Unimplemented
Unimplemented
Unimplemented
CREN
Unimplemented
Unimplemented
Unimplemented
CHS2
INTE
Bit 4
Write Buffer for the upper 5 bits of the Program Counter
TXIF
RA4
RB4
RC4
CKP
TO
B1
TOUTPS0
CCP1M3
ADDEN
SSPM3
RABIE
SSPIF
CHS1
Bit 3
RA3
RC3
PD
—
—
PIC16F/LF720/721
TMR2ON
CCP1M2
T1SYNC
TMR0IF
CCP1IF
SSPM2
FERR
CHS0
Bit 2
RA2
RC2
—
Z
T2CKPS1 T2CKPS0
CCP1M1
TMR2IF
SSPM1
OERR
DONE
Bit 1
INTF
RA1
RC1
GO/
DC
—
—
TMR1ON
CCP1M0
TMR1IF
SSPM0
RABIF
ADON
RX9D
Bit 0
RC0
RA0
—
C
DS41430A-page 17
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
--xx xxxx
xxxx ----
xxxx xxxx
---0 0000
0000 000x
0000 0000
xxxx xxxx
xxxx xxxx
0000 -0-0
0000 0000
-000 0000
xxxx xxxx
0000 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 000x
0000 0000
0000 0000
xxxx xxxx
--00 0000
POR, BOR
Value on
—
—
—
—
—
—
Value on all
xxxx xxxx
uuuu uuuu
0000 0000
000q quuu
uuuu uuuu
--xx xxxx
uuuu ----
uuuu uuuu
---0 0000
0000 000x
0000 0000
uuuu uuuu
uuuu uuuu
uuuu -u-u
0000 0000
-000 0000
uuuu uuuu
0000 0000
uuuu uuuu
uuuu uuuu
--00 0000
0000 000x
0000 0000
0000 0000
uuuu uuuu
--00 0000
Resets
other
—
—
—
—
—
—