PIC16F721T-I/ML Microchip Technology, PIC16F721T-I/ML Datasheet - Page 19

• Manufacturer Part Number: PIC16F721T-I/ML
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 QFN 4x4mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721T-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

TABLE 2-1:
 2010 Microchip Technology Inc.
100h
101h
102h
103h
104h
105h
106h
107h
108h
109h
10Ah
10Bh
10Ch
10Dh
10Eh
10Fh
110h
111h
112h
113h
114h
115h
116h
117h
118h
119h
11Ah
11Bh
11Ch
11Dh
11Eh
11Fh
Legend:
Note 1:
Address
Bank 2
(
(
(
(
(
(
2
2
2
2
1
2
2:
3:
4:
5:
)
)
)
)
),(
)
2
)
The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8>, whose contents are transferred to the
upper byte of the program counter.
These registers can be addressed from any bank.
Accessible only when SSPM<3:0> = 1001.
This bit is unimplemented and reads as ‘1’.
See
INDF
TMR0
PCL
STATUS
FSR
PCLATH
INTCON
PMDATL
PMADRL
PMDATH
PMADRH
WPUB
IOCB
x = unknown, u = unchanged, q = value depends on condition, - = unimplemented, read as ‘0’, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Register
Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
6-2.
WPUB7
IOCB7
Bit 7
IRP
GIE
—
—
—
Addressing this location uses contents of FSR to address data memory (not a physical register)
WPUB6
IOCB6
Bit 6
PEIE
RP1
—
—
—
Program Memory Read Address Register Low Byte
Program Memory Read Data Register Low Byte
TMR0IE
WPUB5
Program Counter (PC) Least Significant Byte
IOCB5
Bit 5
RP0
—
—
Indirect Data Memory Address Pointer
Timer0 module Register
Write Buffer for the upper 5 bits of the Program Counter
Program Memory Read Data Register High Byte
WPUB4
IOCB4
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
INTE
Bit 4
TO
Program Memory Read Address Register High Byte
RABIE
Bit 3
PD
—
—
PIC16F/LF720/721
TMR0IF
Bit 2
—
—
Z
Bit 1
INTF
DC
—
—
RABIF
Bit 0
—
—
C
DS41430A-page 19
xxxx xxxx
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
---0 0000
0000 000x
xxxx xxxx
0000 0000
--xx xxxx
---0 0000
1111 ----
0000 ----
POR, BOR
Value on
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Value on all
xxxx xxxx
uuuu uuuu
0000 0000
000q quuu
uuuu uuuu
---0 0000
0000 000x
xxxx xxxx
0000 0000
--xx xxxx
---0 0000
1111 ----
0000 ----
Resets
other
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—