PIC16F721T-I/ML Microchip Technology, PIC16F721T-I/ML Datasheet - Page 95

• Manufacturer Part Number: PIC16F721T-I/ML
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 QFN 4x4mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721T-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

13.0
The Timer1 module is a 16-bit timer/counter with the
following features:
• 16-bit timer/counter register pair (TMR1H:TMR1L)
• Programmable internal or external clock source
• 3-bit prescaler
• Synchronous or asynchronous operation
• Multiple Timer1 gate (count enable) sources
• Interrupt on overflow
• Wake-up on overflow (external clock,
• Time base for the Capture/Compare function
• Special Event Trigger (with CCP)
• Selectable Gate Source Polarity
FIGURE 13-1:
 2010 Microchip Technology Inc.
From WDT
Overflow
From Timer2
Asynchronous mode only)
T1G
From Timer0
Note 1: ST buffer is high speed type when using T1CKI.
Match PR2
Overflow
T1GSS<1:0>
2: Timer1 register increments on rising edge.
3: Synchronize does not operate while in Sleep.
TIMER1 MODULE WITH GATE
CONTROL
T1GPOL
TMR1ON
T1GTM
Set flag bit
TMR1IF on
Overflow
00
10
11
01
TIMER1 BLOCK DIAGRAM
T1CKI
TMR1H
TMR1
T1G_IN
(2)
D
R
CK
TMR1L
Q
Q
(1)
TMR1CS<1:0>
Reserved
Internal
F
Internal
Clock
Clock
F
OSC
0
1
OSC
T1GGO/DONE
Q
/4
EN
D
• Gate Toggle Mode
• Gate Single-pulse Mode
• Gate Value Status
• Gate Event Interrupt
Figure 13-1
Single Pulse
Acq. Control
10
11
00
01
T1CLK
T1GSPM
PIC16F/LF720/721
T1CKPS<1:0>
T1SYNC
Prescaler
1, 2, 4, 8
TMR1ON
is a block diagram of the Timer1 module.
0
1
2
0
1
Internal
F
Clock
OSC
T1GVAL
TMR1GE
/2
Q1
Synchronized
Synchronize
Interrupt
clock input
D
EN
det
det
Sleep input
Q
DS41430A-page 95
(3)
Set
TMR1GIF
Data Bus
T1GCON
RD