PIC16F721T-I/ML Microchip Technology, PIC16F721T-I/ML Datasheet - Page 39

• Manufacturer Part Number: PIC16F721T-I/ML
• Description: 7 KB FLASH, 256 B SRAM, 18 I/O 20 QFN 4x4mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 16Fr

Specifications of PIC16F721T-I/ML

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 17
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 12x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.3
Some interrupts can be used to wake from Sleep. To
wake from Sleep, the peripheral must be able to
operate without the system clock. The interrupt source
must have the appropriate Interrupt Enable bit(s) set
prior to entering Sleep.
On waking from Sleep, if the GIE bit is also set, the
processor will branch to the interrupt vector. Otherwise,
the processor will continue executing instructions after
the SLEEP instruction. The instruction directly after the
SLEEP instruction will always be executed before
branching to the ISR. Refer to the
“Power-Down Mode (Sleep)”
4.4
The
asynchronous, edge-triggered interrupt. The INTEDG bit
of the OPTION register determines on which edge the
interrupt will occur. When the INTEDG bit is set, the
rising edge will cause the interrupt. When the INTEDG
bit is clear, the falling edge will cause the interrupt. The
INTF bit of the INTCON register will be set when a valid
edge appears on the INT pin. If the GIE and INTE bits
are also set, the processor will redirect program
execution to the interrupt vector. This interrupt is
disabled by clearing the INTE bit of the INTCON register.
4.5
When an interrupt occurs, only the return PC value is
saved to the stack. If the ISR modifies or uses an
instruction that modifies key registers, their values
must be saved at the beginning of the ISR and restored
when the ISR completes. This prevents instructions
EXAMPLE 4-1:
 2010 Microchip Technology Inc.
MOVWFW_TEMP
SWAPFSTATUS,W
BANKSELSTATUS_TEMP ;Select regardless of current bank
MOVWFSTATUS_TEMP
MOVF
MOVWF
:
:(ISR)
:
BANKSELSTATUS_TEMP ;Select regardless of current bank
MOVF
MOVWF
SWAPFSTATUS_TEMP,W ;Swap STATUS_TEMP register into W
MOVWFSTATUS
SWAPFW_TEMP,F
SWAPFW_TEMP,W
external
Interrupts During Sleep
INT Pin
Context Saving
PCLATH,W
PCLATH_TEMP
PCLATH_TEMP,W;
PCLATH
interrupt,
SAVING W, STATUS AND PCLATH REGISTERS IN RAM
;Copy W to W_TEMP register
;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
;Copy status to bank zero STATUS_TEMP register
;Copy PCLATH to W register
;Insert user code here
;Restore PCLATH
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
INT
for more details.
;Copy W register to PCLATH_TEMP
pin,
Section 19.0
causes
an
following the ISR from using invalid data. Examples of
key registers include the W, STATUS, FSR and
PCLATH registers.
The code shown in
following.
• Save the W register
• Save the STATUS register
• Save the PCLATH register
• Execute the ISR program
• Restore the PCLATH register
• Restore the STATUS register
• Restore the W register
Since most instructions modify the W register, it must
be saved immediately upon entering the ISR. The
SWAPF instruction is used when saving and restoring
the W and STATUS registers because it will not affect
any bits in the STATUS register. It is useful to place
W_TEMP in shared memory because the ISR cannot
predict which bank will be selected when the interrupt
occurs.
The processor will branch to the interrupt vector by
loading the PC with 0004h. The PCLATH register will
remain unchanged. This requires the ISR to ensure
that the PCLATH register is set properly before using
an instruction that causes PCLATH to be loaded into
the PC. See
details on PC operation.
Note:
PIC16F/LF720/721
The microcontroller does not normally
require saving the PCLATH register.
However, if computed GOTOs are used,
the PCLATH register must be saved at the
beginning of the ISR and restored when
the ISR is complete to ensure correct
program flow.
Section 2.3 “PCL and PCLATH”
Example 4-1
can be used to do the
DS41430A-page 39
for