PIC32MX360F512LT-80I/BG Microchip Technology, PIC32MX360F512LT-80I/BG Datasheet - Page 56
PIC32MX360F512LT-80I/BG
Manufacturer Part Number
PIC32MX360F512LT-80I/BG
Description
512 KB Flash, 32 KB RAM, 80 MHz, 10-Bit ADC, DMA Trace 121 XBGA 10x10x1.20mm T/R
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
Specifications of PIC32MX360F512LT-80I/BG
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Processor Series
PIC32MX3xx
Core
MIPS
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX360F512LT-80I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
- MA320002 PDF datasheet
- DM320001 PDF datasheet #2
- PIC32MX320F032H-40IPT PDF datasheet #3
- PIC32MX320F032H-40IPT PDF datasheet #4
- PIC32MX320F032H-40IPT PDF datasheet #5
- Current page: 56 of 208
- Download datasheet (5Mb)
TABLE 4-9:
Legend:
Note
3000 OC1CON
3010
3020
3200 OC2CON
3210
3220
3400 OC3CON
3410
3420
3600 OC4CON
3610
3620
3800 OC5CON
3810
3820
1:
OC1RS
OC2RS
OC3RS
OC4RS
OC5RS
OC1R
OC2R
OC3R
OC4R
OC5R
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
OUTPUT COMPARE1-5 REGISTERS MAP
31/15
ON
ON
ON
ON
ON
—
—
—
—
—
30/14
FRZ
FRZ
FRZ
FRZ
FRZ
—
—
—
—
—
29/13
SIDL
SIDL
SIDL
SIDL
SIDL
—
—
—
—
—
28/12
—
—
—
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
—
—
—
26/10
—
—
—
—
—
—
—
—
—
—
(1)
25/9
—
—
—
—
—
—
—
—
—
—
24/8
OC1RS<31:0>
OC2RS<31:0>
OC3RS<31:0>
OC4RS<31:0>
OC5RS<31:0>
—
—
—
—
—
—
—
—
—
—
OC1R<31:0>
OC2R<31:0>
OC3R<31:0>
OC4R<31:0>
OC5R<31:0>
Bits
23/7
—
—
—
—
—
—
—
—
—
—
22/6
—
—
—
—
—
—
—
—
—
—
OC32
OC32
OC32
OC32
OC32
21/5
—
—
—
—
—
OCFLT
OCFLT
OCFLT
OCFLT
OCFLT
20/4
—
—
—
—
—
OCTSEL
OCTSEL
OCTSEL
OCTSEL
OCTSEL
19/3
—
—
—
—
—
18/2
—
—
—
—
—
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
OCM<2:0>
17/1
—
—
—
—
—
16/0
—
—
—
—
—
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
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