PIC32MX360F512LT-80I/BG Microchip Technology, PIC32MX360F512LT-80I/BG Datasheet - Page 68

• Manufacturer Part Number: PIC32MX360F512LT-80I/BG
• Description: 512 KB Flash, 32 KB RAM, 80 MHz, 10-Bit ADC, DMA Trace 121 XBGA 10x10x1.20mm T/R
• Manufacturer: Microchip Technology
• Series: PIC® 32MXr

Specifications of PIC32MX360F512LT-80I/BG

• Core Processor: MIPS32® M4K™
• Core Size: 32-Bit
• Speed: 80MHz
• Connectivity: I²C, IrDA, LIN, PMP, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.3 V ~ 3.6 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 121-TFBGA
• Processor Series: PIC32MX3xx
• Core: MIPS
• 3rd Party Development Tools: 52713-733, 52714-737
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of I /o: -
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

TABLE 4-20:
Legend:
Note
F000 OSCCON
F010 OSCTUN
F600
F610 RSWRST
0000 WDTCON
1:
2:
RCON
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
All registers in this table have corresponding CLR, SET and INV Registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
Reset values are dependent on the DEVCFGx Configuration bits and the type of reset.
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
SYSTEM CONTROL REGISTERS MAP
31/15
ON
—
—
—
—
—
—
—
—
—
30/14
—
—
—
—
—
—
—
—
—
COSC<2:0>
29/13
—
—
—
—
—
—
—
—
PLLODIV<2:0>
28/12
—
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
—
—
(1,2)
26/10
—
—
—
—
—
—
—
—
RCDIV<2:0>
NOSC<2:0>
CMR
25/9
—
—
—
—
—
—
—
VREGS
24/8
—
—
—
—
—
—
—
Bits
CLKLOCK
EXTR
23/7
—
—
—
—
—
—
—
—
SOSCRDY
ULOCK
SWR
22/6
—
—
—
—
—
—
LOCK
21/5
—
—
—
—
—
—
—
SWDTPS<4:0>
SLPEN
WDTO
20/4
—
—
—
—
—
PBDIV<1:0>
SLEEP
19/3
CF
—
—
—
—
—
TUN<5:0>
UFRCEN
IDLE
18/2
—
—
—
—
—
PLLMULT<2:0>
SOSCEN
17/1
BOR
—
—
—
—
—
—
WDTCLR 0000
OSWEN
SWRST
POR
16/0
—
—
—
—
0000
0000
0000
0000
0000
0000
0000
0000
0000