PIC32MX360F512LT-80I/BG Microchip Technology, PIC32MX360F512LT-80I/BG Datasheet - Page 78
PIC32MX360F512LT-80I/BG
Manufacturer Part Number
PIC32MX360F512LT-80I/BG
Description
512 KB Flash, 32 KB RAM, 80 MHz, 10-Bit ADC, DMA Trace 121 XBGA 10x10x1.20mm T/R
Manufacturer
Microchip Technology
Series
PIC® 32MXr
Datasheets
1.MA320002.pdf
(208 pages)
2.DM320001.pdf
(44 pages)
3.PIC32MX320F032H-40IPT.pdf
(48 pages)
4.PIC32MX320F032H-40IPT.pdf
(66 pages)
5.PIC32MX320F032H-40IPT.pdf
(22 pages)
Specifications of PIC32MX360F512LT-80I/BG
Core Processor
MIPS32® M4K™
Core Size
32-Bit
Speed
80MHz
Connectivity
I²C, IrDA, LIN, PMP, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.3 V ~ 3.6 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
121-TFBGA
Processor Series
PIC32MX3xx
Core
MIPS
3rd Party Development Tools
52713-733, 52714-737
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, DM320001, DM320002, MA320001
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of I /o
-
Eeprom Size
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC32MX360F512LT-80I/BG
Manufacturer:
Microchip Technology
Quantity:
10 000
- MA320002 PDF datasheet
- DM320001 PDF datasheet #2
- PIC32MX320F032H-40IPT PDF datasheet #3
- PIC32MX320F032H-40IPT PDF datasheet #4
- PIC32MX320F032H-40IPT PDF datasheet #5
- Current page: 78 of 208
- Download datasheet (5Mb)
TABLE 4-39:
Legend:
Note
40A0
40C0 CHEPFABT
4000 CHECON
4010 CHEACC
4020 CHETAG
4030 CHEMSK
4040
4050
4060
4070
4080
4090
1:
CHELRU
CHEMIS
CHEW0
CHEW1
CHEW2
CHEW3
CHEHIT
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
This register has corresponding CLR, SET and INV Registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
(1)
(1)
(1)
(1)
31:16
31:16 CHEWEN
31:16 LTAGBOOT
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
31:16
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
15:0
PREFETCH REGISTERS MAP
31/15
—
—
—
—
—
30/14
—
—
—
—
—
—
—
29/13
—
—
—
—
—
—
—
28/12
—
—
—
—
—
—
—
27/11
—
—
—
—
—
—
—
LMASK<15:5>
26/10
—
—
—
—
—
—
—
LTAG<15:4>
25/9
—
—
—
—
—
—
DCSZ<1:0>
CHEPFABT<31:0>
CHELRU<15:0>
24/8
CHEMIS<31:0>
CHEW0<31:0>
CHEW1<31:0>
CHEW2<31:0>
CHEW3<31:0>
CHEHIT<31:0>
—
—
—
—
—
Bits
23/7
—
—
—
—
—
22/6
—
—
—
—
—
21/5
PREFEN<1:0>
—
—
—
—
CHELRU<24:16>
20/4
—
—
—
—
—
LTAG<23:16>
LVALID
19/3
—
—
—
—
—
LLOCK
18/2
—
—
CHEIDX<3:0>
—
—
PFMWS<2:0>
LTYPE
17/1
—
—
—
—
CHECOH 0000
16/0
—
—
—
—
0000
0000
00xx
xxx0
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
0000
0000
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
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