STM32F100RET6B STMicroelectronics, STM32F100RET6B Datasheet - Page 15
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
STM32F100RET6B
Manufacturer Part Number
STM32F100RET6B
Description
16/32-BITS MICROS
Manufacturer
STMicroelectronics
Series
STM32r
Datasheet
1.STM32F100RCT6TR.pdf
(97 pages)
Specifications of STM32F100RET6B
Core Processor
ARM® Cortex-M3™
Core Size
32-Bit
Speed
24MHz
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
DMA, PDR, POR, PVD, PWM, Temp Sensor, WDT
Number Of I /o
51
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Eeprom Size
-
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 16x12b; D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
STM32F100RET6B
Manufacturer:
NXP
Quantity:
11 430
Company:
Part Number:
STM32F100RET6B
Manufacturer:
STMicroelectronics
Quantity:
10 000
Company:
Part Number:
STM32F100RET6BTR
Manufacturer:
STMicroelectronics
Quantity:
10 000
STM32F100xC, STM32F100xD, STM32F100xE
2.2.11
2.2.12
2.2.13
2.2.14
The boot loader is located in System Memory. It is used to reprogram the Flash memory by
using USART1. For further details please refer to AN2606.
Power supply schemes
●
●
●
Power supply supervisor
The device has an integrated power on reset (POR)/power down reset (PDR) circuitry. It is
always active, and ensures proper operation starting from/down to 2 V. The device remains
in reset mode when V
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
V
generated when V
than the V
message and/or put the MCU into a safe state. The PVD is enabled by software.
Voltage regulator
The regulator has three operation modes: main (MR), low power (LPR) and power down.
●
●
●
This regulator is always enabled after reset. It is disabled in Standby mode, providing high
impedance output.
Low-power modes
The STM32F100xx value line supports three low-power modes to achieve the best
compromise between low power consumption, short startup time and available wakeup
sources:
●
●
DD
/V
V
Provided externally through V
V
RCs and PLL (minimum voltage to be applied to V
used).
V
V
registers (through power switch) when V
MR is used in the nominal regulation mode (Run)
LPR is used in the Stop mode
Power down is used in Standby mode: the regulator output is in high impedance: the
kernel circuitry is powered down, inducing zero consumption (but the contents of the
registers and SRAM are lost)
Sleep mode
In Sleep mode, only the CPU is stopped. All peripherals continue to operate and can
wake up the CPU when an interrupt/event occurs.
Stop mode
Stop mode achieves the lowest power consumption while retaining the content of
SRAM and registers. All clocks in the 1.8 V domain are stopped, the PLL, the HSI RC
and the HSE crystal oscillators are disabled. The voltage regulator can also be put
DD
SSA
DDA
BAT
DDA
= 2.0 to 3.6 V: External power supply for I/Os and the internal regulator.
, V
= 1.8 to 3.6 V: Power supply for RTC, external clock 32 kHz oscillator and backup
PVD
power supply and compares it to the V
and V
DDA
threshold. The interrupt service routine can then generate a warning
SSA
= 2.0 to 3.6 V: External analog power supplies for ADC, DAC, Reset blocks,
DD
must be connected to V
/V
DD
DDA
is below a specified threshold, V
drops below the V
Doc ID 15081 Rev 5
DD
pins.
DD
DD
PVD
and V
is not present.
PVD
threshold and/or when V
SS
threshold. An interrupt can be
DDA
, respectively.
POR/PDR
is 2.4 V when the ADC or DAC is
, without the need for an
DD
/V
DDA
Description
is higher
15/97