ISP1507FBS,518 NXP Semiconductors, ISP1507FBS,518 Datasheet - Page 24

• Manufacturer Part Number: ISP1507FBS,518
• Description: RF Transceiver USB 2.0 ULPI TRNSCVR
• Manufacturer: NXP Semiconductors

Specifications of ISP1507FBS,518

• Number Of Transceivers: 1
• Esd Protection: YeskV
• Power Supply Requirement: Single
• Operating Supply Voltage (typ): 3.3V
• Operating Temperature Classification: Industrial
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 3V
• Dual Supply Voltage (typ): Not RequiredV
• Dual Supply Voltage (max): Not RequiredV
• Dual Supply Voltage (min): Not RequiredV
• Mounting: Surface Mount
• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Lead Free Status / RoHS Status: Compliant
• Other names: 935285499518 ISP1507FBS-T

NXP Semiconductors
ISP1507E_ISP1507F_1
Product data sheet
Fig 7.
DATA[3:0]
RESET_N
CLOCK
NXT
STP
DIR
Interface behavior with respect to RESET_N
9.3.2 Interface behavior with respect to RESET_N
9.4.1 Driving 5 V on V
9.4 V
Hi-Z (input)
Hi-Z (input)
The interface protect feature can be disabled by setting the INTF_PROT_DIS bit to logic 1.
The use of the RESET_N pin is optional. When RESET_N is asserted (LOW), the
ISP1507 will assert DIR. All logic in the ISP1507 will be reset, including the analog
circuitry and ULPI registers. During reset, the link must drive DATA[3:0] and STP to LOW;
otherwise undefined behavior may result. When RESET_N is deasserted (HIGH), the DIR
output will deassert (LOW) four or five clock cycles later.
behavior when RESET_N is asserted (LOW), and subsequently deasserted (HIGH). If
RESET_N is not used, it must be connected to V
The ISP1507 provides a built-in charge pump. To enable the charge pump, the link must
set the DRV_VBUS bit in the OTG_CTRL register (see
The ISP1507 also supports external 5 V supplies. The ISP1507 can control the external
supply using the active-LOW PSW_N open-drain output pin. To enable the external supply
by driving PSW_N to LOW, the link must set the DRV_VBUS_EXT bit in the OTG_CTRL
register to logic 1. The link can optionally set both the DRV_VBUS and DRV_VBUS_EXT
bits to logic 1 to enable the external supply.
Table 8
Table 8.
DRV_VBUS
0
1
X
BUS
power and fault detection
summarizes settings to drive 5 V on V
OTG_CTRL register power control bits
Hi-Z (link must drive)
Hi-Z (link must drive)
DRV_VBUS_EXT
0
0
1
BUS
Rev. 01 — 28 May 2008
Power source used
internal and external V
internal V
external 5 V V
Hi-Z (input)
Hi-Z (input)
BUS
BUS
ISP1507E; ISP1507F
CC(I/O)
charge pump is enabled
.
BUS
supply is enabled
.
Section
Figure 7
ULPI HS USB OTG transceiver
BUS
power sources are disabled
10.1.4).
shows the ULPI
© NXP B.V. 2008. All rights reserved.
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