MMA7455LR2 Freescale, MMA7455LR2 Datasheet - Page 26

• Manufacturer Part Number: MMA7455LR2
• Manufacturer: Freescale

Specifications of MMA7455LR2

• Family Name: MMA7455L
• Package Type: LGA
• Operating Supply Voltage (min): 2.4V
• Operating Supply Voltage (typ): 2.8V
• Operating Supply Voltage (max): 3.6V
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Operating Temperature Classification: Industrial
• Product Depth (mm): 3mm
• Product Height (mm): 1mm
• Product Length (mm): 5mm
• Mounting: Surface Mount
• Pin Count: 14
• Lead Free Status / RoHS Status: Compliant

Table 12. Configuring the Interrupt settings using Register $18 with INTREG[1:0] bits
$17: Interrupt Latch Reset (Read/Write)
CLR_INT1
CLR_INT2
00: INT1 Register is detecting Level while INT2 is detecting Pulse.
01: INT1 Register is detecting Pulse while INT2 is detecting Level.
10: INT1 Register is detecting a Single Pulse and INT2 is detecting Single Pulse (if 2
time window and second time window > 0 then INT2 will detect the double pulse only.
INTPIN: INT1 pin is routed to INT1 bit in Detection Source Register ($0A) and INT2 pin is routed to INT2 bit in Detection Source
Register ($0A).
INTPIN: INT2 pin is routed to INT1 bit in Detection Source Register ($0A) and INT1 pin is routed to INT2 bit in Detection Source
Register ($0A).
XDA
1: X-axis is disabled for detection.
0: X-axis is enabled for detection.
YDA
1: Y-axis is disabled for detection.
0: Y-axis is enabled for detection.
ZDA
1: Z-axis is disabled for detection.
0: Z-axis is enabled for detection.
$19: Control 2 (Read/Write)
LDPL
0: Level detection polarity is positive and detecting condition
is OR 3 axes.
1: Level detection polarity is negative detecting condition is
AND 3 axes.
$18 Control 1 (Read/Write)
26
MMA7455L
DFBW
D7
D7
D7
--
0
0
0
INTREG[1:0]
1: Clear “INT1” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in Detection Source Register ($0A) depending on
Control1($18) INTREG[1:0] setting.
0: Do not clear “INT1” LDX/LDY/LDZ or PDX/PDY/PDZ bits in Detection Source Register ($0A)
1: Clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in Detection Source Register ($0A) depending on
Control1($18) INTREG[1:0] setting.
0: Do not clear “INT2” and LDX/LDY/LDZ or PDX/PDY/PDZ bits in Detection Source Register ($0A).
00
01
10
THOPT
D6
D6
D6
--
0
0
0
ZDA
D5
D5
D5
--
0
0
0
Single Pulse detection
“INT1” Register Bit
Pulse Detection
Level detection
YDA
D4
D4
D4
--
0
0
0
XDA
D3
D3
D3
0
--
0
0
THOPT (This bit is valid for level detection only, not valid
DFBW
0: Digital filter band width is 62.5 Hz
1: Digital filter band width is 125 Hz
PDPL
0: Pulse detection polarity is positive and detecting condition
is OR 3 axes.
1: Pulse detection polarity is negative and detecting condition
is AND 3 axes.
DRVO
0: Standard drive strength on SDA/SDO pin
1: Strong drive strength on SDA/SDO pin
0: Threshold value is absolute only
1: Integer value is available.
for pulse detection)
INTREG[1]
DRVO
D2
D2
D2
0
--
0
0
nd
Time Window = 0) or if there is a latency
INTREG[0]
CLR_INT2
Single or Double Pulse Detection
PDPL
D1
D1
D1
0
0
0
“INT2” Register Bit
Pulse Detection
Level Detection
CLR_INT1
Freescale Semiconductor
INTPIN
LDPL
D0
D0
D0
0
0
0
Function
Function
Function
Default
Default
Default
Bit
Bit
Bit
Sensors