MT49H32M9FM-33 IT Micron Technology Inc, MT49H32M9FM-33 IT Datasheet - Page 37

• Manufacturer Part Number: MT49H32M9FM-33 IT
• Manufacturer: Micron Technology Inc
• Type: RLDRAMr

Specifications of MT49H32M9FM-33 IT

• Organization: 32Mx9
• Density: 288Mb
• Address Bus: 22b
• Maximum Clock Rate: 300MHz
• Operating Supply Voltage (typ): 1.8V
• Package Type: uBGA
• Operating Temp Range: -40C to 85C
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Supply Current: 609mA
• Pin Count: 144
• Mounting: Surface Mount
• Operating Temperature Classification: Industrial
• Lead Free Status / RoHS Status: Not Compliant

DLL RESET
Drive Impedance Matching
On-Die Termination (ODT)
PDF: 09005aef80a41b46/Source: 09005aef809f284b
RLDRAM_II_CIO_Core.fm - Rev. D 12/10 EN
needing a maximum of 11 address balls to control the RLDRAM, reducing the number of
signals on the controller side. The data bus efficiency in continuous burst mode is only
affected when using the BL = 2 setting since the device requires two clocks to read and
write the data. The bank addresses are delivered to the RLDRAM at the same time as the
WRITE and READ command and the first address part, Ax. Table 22 on page 62 shows
the addresses needed for both the first and second rising clock edges (Ax and Ay, respec-
tively). The AREF command does not require an address on the second rising clock edge,
as only the bank address is needed during this command. Because of this, AREF
commands may be issued on consecutive clocks.
The multiplexed address option is available by setting bit M5 to “1” in the mode register.
Once this bit is set, the READ, WRITE, and MRS commands follow the format described
in Figure 34 on page 59. Further information on operation with multiplexed addresses
can be seen in "Multiplexed Address Mode" on page 59.
DLL RESET is selected with bit M7 of the mode register as is shown in Figure 10 on
page 34. The default setting for this option is LOW, whereby the DLL is disabled. Once
M7 is set HIGH, 1,024 cycles (5µs at 200 MHz) are needed before a READ command can
be issued. This time allows the internal clock to be synchronized with the external clock.
Failing to wait for synchronization to occur may result in a violation of the
parameter. A reset of the DLL is necessary if
already been enabled. To reset the DLL, an MRS command must be issued where M7 is
set LOW. After waiting
M7 goes HIGH. 1,024 clock cycles are then needed before a READ command is issued.
The RLDRAM II is equipped with programmable impedance output buffers. This option
is selected by setting bit M8 HIGH during the MRS command. The purpose of the
programmable impedance output buffers is to allow the user to match the driver imped-
ance to the system. To adjust the impedance, an external precision resistor (RQ) is
connected between the ZQ ball and Vss. The value of the resistor must be five times the
desired impedance. For example, a 300Ω resistor is required for an output impedance of
60Ω. The range of RQ is 125–300Ω, which guarantees output impedance in the range of
25–60Ω (within 15%).
Output impedance updates may be required because over time variations may occur in
supply voltage and temperature. When the external drive impedance is enabled in the
MRS, the device will periodically sample the value of RQ. An impedance update is trans-
parent to the system and does not affect device operation. All data sheet timing and
current specifications are met during an update.
When bit M8 is set LOW during the MRS command, the RLDRAM provides an internal
impedance at the output buffer of 50Ω (±30% with temperature variation). This imped-
ance is also periodically sampled and adjusted to compensate for variation in supply
voltage and temperature.
ODT is enabled by setting M9 to “1” during an MRS command. With ODT on, the DQs
and DM are terminated to V
clock signals are not terminated. Figure 12 on page 38 shows the equivalent circuit of a
DQ receiver with ODT. The ODT function is dynamically switched off when a DQ begins
288Mb: x9, x18, x36 2.5V V
t
MRSC, a subsequent MRS command should be issued whereby
TT
37
with a resistance Rtt. The command, address, QVLD, and
Micron Technology, Inc., reserves the right to change products or specifications without notice.
EXT
t
CK or V
, 1.8V V
DD
is changed after the DLL has
DD
, HSTL, CIO, RLDRAM II
©2004 Micron Technology, Inc. All rights reserved.
Commands
t
CKQK