FW82801BA S L5PN Intel, FW82801BA S L5PN Datasheet - Page 242

• Manufacturer Part Number: FW82801BA S L5PN
• Manufacturer: Intel

Specifications of FW82801BA S L5PN

• Lead Free Status / RoHS Status: Not Compliant

Functional Description
5.21.1.2
242
Table 115. Block Write–Block Read Process Call Protocol with/without PEC (Sheet 2 of 2)
Note: When operating in I
I
When the I
devices. This forces the following changes:
In addition, the ICH5 will support the new I
bit.
2
•
•
C Behavior
Bit
The Process Call command will skip the Command code (and its associated acknowledge)
The Block Write command will skip sending the Byte Count (DATA0)
–
2
Repeated Start
Slave Address — 7 bits
Read
Acknowledge from master
Data Byte Count (N) from master — 8 bits
Acknowledge from slave
Data Byte (1) from master — 8 bits
Acknowledge from slave
Data Byte (2) from master — 8 bits
Acknowledge from slave
–
Data Byte Count (N) from master — 8 bits
Acknowledge from slave
Data Byte High from slave - 8 bits
Acknowledge from slave (Skip if no PEC)
PEC from master (Skip if no PEC)
NOT acknowledge
Stop
C_EN bit is set, the ICH5 SMBus logic will instead be set to communicate with I
2
C mode the ICH5 will not use the 32-byte buffer for block commands.
Description
2
C Read command. This is independent of the I
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
2
C_EN
2
C