FW82801BA S L5PN Intel, FW82801BA S L5PN Datasheet - Page 260
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FW82801BA S L5PN
Manufacturer Part Number
FW82801BA S L5PN
Description
Manufacturer
Intel
Datasheet
1.FW82801BA_S_L5PN.pdf
(671 pages)
Specifications of FW82801BA S L5PN
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Functional Description
5.22.2.16
5.22.2.17 Input Slot 3: PCM Record Left Channel
5.22.2.18
5.22.2.19
260
Table 127. Input Slot 1 Bit Definitions
Input Slot 2: Status Data Port
Input Slot 4: PCM Record Right Channel
Input Slot 5: Modem Line
NOTES:
As shown in
slot request flags for all output slots of the controller. When a slot request bit is set by the codec, the
controller returns data in that slot in the next output frame. Slot request bits for slots 3 and 4 are
always set or cleared in tandem (i.e., both are set or cleared).
When set, the input slot 1 tag bit only pertains to Status Address Port data from a previous read.
SLOTREQ bits are always valid independent of the slot 1 tag bit.
The status data port receives 16-bit control register read data.
Bit [19:4]: Control Register Read Data
Bit [3:0]:
Input slot 3 is the left channel input of the codec. The ICH5 supports 16-bit sample resolution.
Samples transmitted to the ICH5 must be in left/right channel order.
Input slot 4 is the right channel input of the codec. The ICH5 supports 16-bit sample resolution.
Samples transmitted to the ICH5 must be in left/right channel order.
Input slot 5 contains MSB justified modem data. The ICH5 supports 16-bit sample resolution.
1. Slot 3 Request and Slot 4 Request bits must be the same value, i.e. set or cleared in tandem. This is also true
18:12
for the Slot 7 and Slot 8 Request bits, as well as the Slot 6 and Slot 9 Request bits.
4:2
1:0
Bit
19
10
11
9
8
7
6
5
Reserved (Set to 0)
Control Register Index (Stuffed with 0s if tagged invalid)
Slot 3 Request: PCM Left Channel
Slot 4 Request: PCM Right Channel
Slot 5 Request: Modem Line 1
Slot 6 Request: PCM Center Channel
Slot 7 Request: PCM Left Surround
Slot 8 Request: PCM Right Surround
Slot 9 Request: PCM LFE Channel
Slot Request 10–12: Not Implemented
Reserved (Stuffed with 0s)
Table
Reserved.
127, slot 1 delivers codec control register read address and multiple sample rate
Description
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Intel
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