FW82801BA S L5PN Intel, FW82801BA S L5PN Datasheet - Page 573
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FW82801BA S L5PN
Manufacturer Part Number
FW82801BA S L5PN
Description
Manufacturer
Intel
Datasheet
1.FW82801BA_S_L5PN.pdf
(671 pages)
Specifications of FW82801BA S L5PN
Lead Free Status / RoHS Status
Not Compliant
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16.2.5
16.2.6
Intel
®
82801EB ICH5 / 82801ER ICH5R Datasheet
x_PICB—Position in Current Buffer Register
(Modem—D31:F6)
I/O Address:
Default Value:
Lockable:
Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit read from
the address offset 08h. Software can also read this register individually by doing a single, 16-bit
read to offset 08h. Reads across DWord boundaries are not supported.
x_PIV—Prefetch Index Value Register
(Modem—D31:F6)
I/O Address:
Default Value:
Lockable:
Software can read the registers at the offsets 08h, 0Ah, and 0Bh by performing a 32-bit read from
the address offset 08h. Software can also read this register individually by doing a single, 8-bit read
to offset 0Ah. Reads across DWord boundaries are not supported.
15:0
7:5
4:0
Bit
Bit
Position In Current Buffer[15:0] — RO. These bits represent the number of samples left to be
processed in the current buffer.
Hardwired to 0.
Prefetched Index Value [4:0] — RO. These bits represent which buffer descriptor in the list has
been prefetched.
MBAR + 08h (MIPICB),
MBAR + 18h (MOPICB),
0000h
No
MBAR + 0Ah (MIPIV),
MBAR + 1Ah (MOPIV)
00h
No
AC ’97 Modem Controller Registers (D31:F6)
Description
Description
Attribute:
Size:
Power Well:
Attribute:
Size:
Power Well:
RO
16 bits
Core
RO
8 bits
Core
573
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