NH82801IO S LAFD Intel, NH82801IO S LAFD Datasheet
NH82801IO S LAFD
Specifications of NH82801IO S LAFD
Related parts for NH82801IO S LAFD
NH82801IO S LAFD Summary of contents
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... ICH9DO, 82801IBM ICH9M, 82801IEM ICH9M-E, and ICH9M- SFF I/O Controller Hubs April 2009 ® Notice: The Intel I/O Controller Hub 9 (ICH9) may contain design defects or errors known as errata which may cause the product to deviate from published specifications. Current characterized errata are available on request. ...
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... BIOS update. Software applications may not be compatible with all operating systems. Please check with your application vendor. Intel Viiv, Intel vPro, Intel SingleDriver, Intel SpeedStep, Intel and the Intel logo are trademarks or registered trademarks of Intel Corporation or its subsidiaries in the United States and other countries. ...
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... Contents—ICH9 Contents Preface ...................................................................................................................... 6 Summary Tables of Changes...................................................................................... 7 Identification Information ......................................................................................... 9 Intel® ICH9 Device and Revision Identification ....................................................... 10 Errata ...................................................................................................................... 12 Specification Changes.............................................................................................. 16 Specification Clarifications ...................................................................................... 17 Documentation Changes .......................................................................................... 18 Specification Update 3 ...
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... Revision History Revision -001 • Initial Release • Added 82801IO ICH9DO specifications • Added following Errata -002 - Errata 4, Intel ICH9 THRM Polarity on SMBus - Errata 5, Intel ICH9 SPI_CS1# State • Added: • - Errata: 6- -003 USB2.0 D+ and D- Maximum Driven Signal Level • - Specification Clarifications: 1- Clarification • ...
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Revision History—ICH9 Revision • Updated Markings Table to include the top marking for ICH9M-SFF part. -012 Added: • Specification Clarifications: 1- Added items: • Document Changes: 5 -Add GPIO Signal Reset Notes, 6- Correct EOIFD bit -013 definition, 7- Update ...
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... This document may also contain information that was not previously published. Affected Documents/Related Documents ® Intel I/O Controller Hub 9 (ICH9) Family Datasheet Nomenclature Errata are design defects or errors. These may cause the Product Name’s behavior to deviate from published specifications ...
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... The following tables indicate the errata, specification changes, specification clarifications, or documentation changes which apply to the Product Name product. Intel may fix some of the errata in a future stepping of the component, and account for the other outstanding issues through documentation or specification changes as noted. ...
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... No Fix Intel ICH9 High-speed USB 2 Fix Intel ICH9 THRM Polarity on SMBus No Fix Intel ICH9 SPI_CS1# State No Fix Intel ICH9 Level-Triggered Legacy IRQ Intel ICH9 High Speed (HS) USB2.0 D+ and D- Maximum Driven X No Fix Signal Level X No Fix PET Alerts on SMBus X No Fix ...
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Summary Tables of Changes Documentation Changes (Sheet No. 10 Update bit definition for SECOND_TO_STS 11 Correct typo for ICH9M-SFF package ball AC22 12 Correct typo in Table 2-22 General Purpose I/O Signals for GPIO[5:2] 13 Correct PCI ...
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... NH82801IB Intel 82801IB ICH9 ® NH82801IR Intel 82801IR ICH9R ® NH82801IH Intel 82801IH ICH9DH ® NH82801IO Intel 82801IO ICH9DO ® AF82801IBM Intel 82801IBM ICH9M ® AF82801IEM Intel 82801IEM ICH9M-E ® AM82801IUX Intel ICH9M-SFF § § Identification Information Notes Specification Update ...
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... Intel® ICH9 Device and Revision Identification ® Intel ICH9 Device and Revision Identification ICH9 Device and Revision ID Table Device Description Function LPC D31:F2 SATA D31:F5 SATA D31:F3 SMBus D31:F6 Thermal DMI to PCI D30:F0 Bridge Specification Update ® Intel ICH9 ICH9 ...
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... Refer to the ICH9 NVM Map and Programming Guide for LAN Device IDs. 3. The SATA RAID Controller Device ID may reflect a different value based on Bit 7 of D31:F2:Offset 9Ch. 12 Intel® ICH9 Device and Revision Identification ® Intel ICH9 ICH9 ICH9 ...
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... None known. Workaround: None. Status: No Fix. For steppings affected, see the Summary Table of Changes. 4. Intel ICH9 THRM Polarity on SMBus Problem: When THRM#_POL (PMBASE+42h:bit0) is set to high, the THRM# pin state as reported to the SMBus TCO unit is logically inverted. Implication: If the THRM#_POL bit is set to high, an external SMBus master reading the BTI Temperature Event status will not receive the correct state of the THRM# pin ...
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... The receiver is pseudo differential design • The receiver is not able to ignore SE1 (single-ended) state Note: Intel has only observed this issue with a motherboard down HS USB 2.0 device using pseudo differential design. This issue will not affect HS USB 2.0 devices with complementary differential design or Low Speed (LS) and Full Speed (FS) devices Workaround: None ...
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... Problem: When using the ICH9 SMBus for Platform Event Trap (PET) alerts on a system with the Intel® Management Engine (ME) enabled, the SMBus packet headers may be corrupted if all of the following conditions are met: • SMBus slave is the target of an external PET generating master on SMBus/SMLink • ...
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... RTC clock cycles due to the pin momentarily being configured as an output GPIO. • LAN_PHY_PWR_CTRL functionality requires a soft strap setting in the SPI descriptor and use of the integrated LAN controller in ICH9M with the Intel® 82567 PHY. Implication: Functional failures such as system hangs or link loss with dropped packets have been observed when LAN_PHY_PWR_CTRL is tied to the LAN_DISABLE_N pin on the Intel® ...
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Specification Changes Specification Changes 1. Clock Slew Rate Change The following change applies to Table 8-9 of the Datasheet. Sym SATA Clock (SATA_CLKP, SATA_CLKN) / DMI Clock (DMI_CLKP, DMI_CLKN) tsatasl Slew rate 2. Serial ATA Clock Request Support. Serial ATA ...
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Specification Clarifications 1. t290 and t294 Clarification a. Note 23 for t290 and t294 in Table 8-22 of the Datasheet is changed as indicated below: 23. t290 and t294 are not applied to V5REF. V5REF timings are bounded by power ...
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Documentation Changes Documentation Changes 1. SATA Interlock Switch State (ISS) Bit Clarification The following change applies to Section 14.4.3.7 of the Datasheet. Interlock Switch State (ISS)— RO. For systems that support interlock switches (via CAP.SIS [ABAR+00h:bit28]), if an interlock switch ...
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... GPIO20 Core GPIO[28:27] Suspend 11 GPIO49 Core GPIO56 Suspend 8. Correct Table 1-5 ICH9M-E Raid Support Make the following correction to Section 1.3 Table 1-5 Intel of the Datasheet: 20 Description with an exception to GPIO signals; refer to section C3/ During Immediately C4/ Reset after Reset C5/C6 UnMultiplexed GPIO Signals ...
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... Support ICH9M Yes ICH9M-E Yes Host Reset without Trigger No Description occurred. If this bit is set and the NO_REBOOT config bit is 0, then the ® Intel Active Management Technology No No Yes Yes Host Reset Global with Power Reset with Power Cycle Power Cycle ...
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... Names TP12 Remove Preliminary from the title of Figure 6-5 and Figure 6-6: Figure 6-5. Intel® ICH9M SFF Ballout(Top View-Left Side) Figure 6-6. Intel® ICH9M SFF Ballout(Top View-Right Side) 12. Correct Typo for Table 2-22 General Purpose I/O Signals for GPIO[5:2] Indicate the proper Note for GPIO[5:2] in Table 2-2 General Purpose I/O Signals for GPIO[5:2] in the Datasheet ...
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... Documentation Changes power (PWROK low Power Button Override event will result in the Intel ICH9 driving a pin to a logic 1 to another device that is powered down. 4. The functionality that is multiplexed with the GPIO may not be utilized in desktop configuration. 5. This GPIO is not an open-drain when configured as an output. ...