NH82801IO S LAFD Intel, NH82801IO S LAFD Datasheet - Page 14

• Manufacturer Part Number: NH82801IO S LAFD
• Manufacturer: Intel

Specifications of NH82801IO S LAFD

• Lead Free Status / RoHS Status: Compliant

Workaround: Available.
Status:
6.
Problem:
Implication:
Workaround: Available.
Status:
7.
Problem:
Implication:
Workaround: None.
Status:
14
Note: Intel has only observed this issue with a motherboard down HS USB 2.0 device using
- When the ICH9 performs its initial read to the SPI device on SPI_CS0#,
1) For ME-enabled systems:
- Desktop: use ME firmware version 3.0.2.xxxx or later, or populate one SPI device.
2) For non-ME systems: populate one SPI device.
No Fix. For steppings affected, see the Summary Table of Changes.
ICH9 Level-Triggered Legacy IRQs
When the ICH9 legacy interrupts [15:0] are configured as level triggered interrupts,
the ICH9 may invert the default interrupt level from high-active to low-active.
Devices or Virtualization SW stacks which use legacy interrupts [15:0] as low-active
level-triggered on the system may see performance degradation due to excessive IRQ
requests.
Note: Intel has not identified any impacted devices or production virtualization system
software stacks (VMMs/OS).
No Fix. For steppings affected, see the Summary Table of Changes
ICH9 High Speed (HS) USB2.0 D+ and D- Maximum Driven Signal
Level
During Start-of-Packet (SOP)/End-of-Packet (EOP), the ICH9 may drive D+ and D- lines
to a level greater than USB 2.0 spec +/-200mV max.
May cause High Speed (HS) USB 2.0 devices to be unrecognized by OS or may not be
readable/writable if the following two conditions are met:
pseudo differential design. This issue will not affect HS USB 2.0 devices with
complementary differential design or Low Speed (LS) and Full Speed (FS) devices
No Fix. For steppings affected, see the Summary Table of Changes.
SPI_CS1# could also be asserted. BIOS may not receive correct boot data.
• For impacted devices: BIOS or Device Driver ensures the ICH9 legacy interrupts
• For impacted Virtualization SW stacks:
• The receiver is pseudo differential design
• The receiver is not able to ignore SE1 (single-ended) state
[15:0] are configured as edge triggered.
— Option 1: Virtualization SW to configure ICH9 legacy interrupt [15:0] as edge
— Option 2: Virtualization SW should mask the low active level triggered interrupt
triggered
allocated to the virtual interrupt by executing the following steps:
. Check if platform is ICH9-based
. If ICH9, check the interrupt polarity specified in the corresponding RTE entry
of IOAPIC. If the polarity is active low, then
a) Mask this line in the physical IOAPIC, and
b) Virtualize the IOAPIC and the corresponding RTE entry mask field to the
guest OS.
Specification Update
Errata