FDC37C78-HT Standard Microsystems (SMSC), FDC37C78-HT Datasheet - Page 16

• Manufacturer Part Number: FDC37C78-HT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C78-HT

• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

DATA RATE SELECT REGISTER (DSR)
Address 3F4 WRITE ONLY
This register is write only. It is used to program
the data rate, amount of write precompensation,
power down status, and software reset. The data
rate is programmed using the Configuration
Control
BIT 0 and 1 DATA RATE SELECT
These bits control the data rate of the floppy
controller.
corresponding to the individual data rates. The
data rate select bits are unaffected by a software
reset, and are set to 250 kbps
reset.
BIT
SELECT
These three bits select the value of write
precompensation that will be applied to the
WDATA output signal.
precompensation values for the combination of
these bits settings. Track 0 is the default starting
track number to start precompensation. this
starting track number can be changed by the
configure command.
BIT 5 UNDEFINED
Should be written as a logic "0".
BIT 6 LOW POWER
A logic "1" written to this bit will put the floppy
controller into Manual Low Power mode. The
2
RESET
COND.
through
See Table 13 for the settings
RESET
S/W
4
Register
7
0
PRECOMPENSATION
Table 12 shows the
POWER
DOWN
6
0
after a hardware
5
0
0
(CCR)
COMP2
PRE-
16
4
0
not the DSR, for PC/AT and Microchannel
applications. Other applications can set the data
rate in the DSR.
controller is the most recent write of either the
DSR or CCR.
software reset. A hardware reset will set the DSR
to 02H, which corresponds to the default
precompensation setting and 250 kbps.
floppy controller clock and data separator circuits
will be turned off. The controller will come out of
manual low power mode after a software reset or
access to the Data Register or Main Status
Register.
BIT 7 SOFTWARE RESET
This active high bit has the same function as the
DOR RESET (DOR bit 2) except that this bit is self
clearing.
PRECOMP
COMP1
PRE-
432
111
001
010
011
100
101
110
000
Table 10 - Precompensation Delays
3
0
COMP0
PRECOMPENSATION DELAY
PRE-
The DSR is unaffected by a
2
0
Default (See Table 14)
The data rate of the floppy
0.00 ns-DISABLED
DRATE
SEL1
125.00 ns
166.67 ns
208.33 ns
250.00 ns
41.67 ns
83.34 ns
1
1
DRATE
SEL0
0
0