FDC37C78-HT Standard Microsystems (SMSC), FDC37C78-HT Datasheet - Page 67

• Manufacturer Part Number: FDC37C78-HT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C78-HT

• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

CR05
This register can only be accessed in
to 05H. The default value after power up is 00H.
CR06
This register can only be accessed in the Configuration Mode and after the CSR has been initialized
to 06H.
disk drive types for up to four floppy disk drives.
CR07
This register can only be accessed in the Configuration Mode and after the CSR has been initialized
to 07H. The default value of this register after power up is 00H. This register holds the value for the auto
power management, polarity of the media ID bits and floppy boot drive information.
BIT NO.
0,1
4,3
2
5
6
7
The default value of this register after power up is FFH. This register holds the floppy
Reserved
FDC DMA Mode
DenSel
Swap Drv 0,1
EXTx4
Reserved
BIT NAME
Table 39 - CR05- Floppy Disk Extended Setup Register
A high level on this bit, swaps drives and motor sel 0 and 1 of the
Read Only. A read returns a 0.
0=(default) Burst mode is enabled for the FDC FIFO execution
phase data transfers. 1=Non-Burst mode enabled. The FDRQ and
FIRQ pins are strobed once for each byte transferred while the FIFO
is enabled.
FDC. A low level on this bit does not (Default).
External 4 drive support: 0=Internal 2 drive decoder (default).
1=External 4 drive decoder (External 2 to 4 decoder required).
Read Only. A read of this bit returns a 0
the Configuration Mode and the CSR has been initialized
Bit 4
0
0
1
1
67
DESCRIPTION
Bit 3
0
1
0
1
Densel output
Normal (Default)
Reserved
1
0