FDC37C78-HT Standard Microsystems (SMSC), FDC37C78-HT Datasheet - Page 66

• Manufacturer Part Number: FDC37C78-HT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C78-HT

• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

CR02
This register can only be accessed in the Configuration Mode and after the CSR has been initialized
to 02H. The default value of this register after power up is 00H.
CR03
This
to 03H. The default value after power up is 70H.
CR04
This register can
to 04H. The default value after power up is 00H.
BIT NO.
BIT NO.
BIT NO.
0
1
2
3
4
5
6
7
0:7
0:7
register
Reserved
Enhanced
Floppy Mode
2
Reserved
Reserved
DRVDEN1
MFM
IDENT
Reserved
BIT NAME
Reserved
can
Reserved
only be accessed in the Configuration Mode and the CSR has been initialized
BIT NAME
BIT NAME
only be accessed in the Configuration Mode and the CSR has been initialized
Reserved - Read as zero
Bit 1
0
1
Reserved - Read as zero
Reserved - Read as zero
IDENT is used in conjunction with MFM to define the interface mode of
operation.
Reserved - Read as zero
0
1
IDENT
1
1
0
0
Read Only. A read returns a 0.
Reserved - Read as zero
DRVDEN 1 output as per DRVDEN table
DRVDEN 1 pin is tri-state (default)
Table 36 - CR02
Table 37 - CR03
Table 38 - CR04
Floppy Mode - Refer to the description of the TAPE
DRIVE REGISTER (TDR) for more information on these
modes.
NORMAL Floppy Mode (Default)
Enhanced Floppy Mode 2 (OS2)
66
MFM
1
0
1
0
DESCRIPTION
DESCRIPTION
DESCRIPTION
MODE
AT Mode (Default)
Reserved
Reserved
Reserved