FDC37C78-HT Standard Microsystems (SMSC), FDC37C78-HT Datasheet - Page 6

• Manufacturer Part Number: FDC37C78-HT
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C78-HT

• Package Type: TQFP
• Lead Free Status / RoHS Status: Compliant

DESCRIPTION OF PIN FUNCTIONS
PIN NO.
44-42
8-11
2-5,
46
47
48
14
13
45
1
Data Bus 0-7
I/O Read
I/O Write
I/O Address
n DMA
Acknowledge
Terminal Count
Interrupt Request IRQ
Chip Select Input nCS
DMA Request
NAME
D0-D7
nIOR
nIOW
A0-A2
DRQ
nDACK
TC
DESCRIPTION OF PIN FUNCTIONS
SYMBOL
HOST PROCESSOR INTERFACE
BUFFER
TYPE
I/O12
O12
O12
I
I
I
I
I
I
6
The data bus connection used by the host
microprocessor to transmit data to and from
the chip. These pins are in a high-impedance
state when not in the output mode.
This active low signal is issued by the host
microprocessor to indicate a read operation.
This active low signal is issued by the host
microprocessor to indicate a write operation.
These host address bits determine the I/O
address to be accessed during nIOR and
nIOW cycles.
internally by the leading edge of nIOR and
nIOW.
This active high output is the DMA request for
byte transfers of data between the host and
the chip. This signal is cleared on the last
byte of the data transfer by the nDACK signal
going low (or by nIOR going low if nDACK
was already low as in demand mode).
An active low input acknowledging the
request for a DMA transfer of data between
the host and the chip. This input enables the
DMA read or write internally.
This signal indicates to the chip that DMA
data transfer is complete.
accepted when nDACK is low. TC is active
high.
The interrupt request from the logical device
is output on the IRQ signal.
configuration registers for more information.
When enabled, this active low pin serves as
an input for an external decoder circuit which
is used to qualify address lines above A2.
DESCRIPTION
These bits are latched
Refer to the
TC is only