FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 148

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

LOGICAL
NUMBER
DEVICE
0x03
0x04
0x05
0x06
0x07
0x08
Note 3: This chip uses ISA address bits [A11:A0] to decode the base address of each of its
logical devices.
Serial Port
Serial Port
LOGICAL
DEVICE
Aux. I/O
Parallel
KYBD
Table 64 - I/O Base Address Configuration Register Description
RTC
Port
1
2
REGISTER
0x60,0x61
0x60,0x61
0x60,0x61
0x60,0x61
0x62,0x63
INDEX
n/a
n/a
the base address is on an 8-
ON 4 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
EPP is only available when
ON 8 BYTE BOUNDARIES
ON 8 BYTE BOUNDARIES
ON 1 BYTE BOUNDARIES
ON 1 BYTE BOUNDARIES
(all modes supported,
(EPP Not supported)
Fixed Base Address
Fixed Base Address
RANGE (NOTE3)
[0x100:0x0FFC]
Not Relocatable
Not Relocatable
[0x100:0x0FF8]
[0x100:0x0FF8]
[0x100:0x0FF8]
byte boundary)
[0x00:0xFFF]
[0x00:0xFFF]
148
BASE I/O
or
+0 : Data|ecpAfifo
+1 : Status
+2 : Control
+3 : EPP Address
+4 : EPP Data 0
+5 : EPP Data 1
+6 : EPP Data 2
+7 : EPP Data 3
+400h : cfifo|ecpDfifo|tfifo
|cnfgA
+401h : cnfgB
+402h : ecr
+0 : RB/TB|LSB div
+1 : IER|MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
+0 : RB/TB|LSB div
+1 : IER|MSB div
+2 : IIR/FCR
+3 : LCR
+4 : MSR
+5 : LSR
+6 : MSR
+7 : SCR
+0 : Address Register
+1 : Data Register
+0 : Data Register
+4 : Command/Status Reg.
+0 : GPR
+0 : GPW
BASE OFFSETS
FIXED