FDC37C935-QS Standard Microsystems (SMSC), FDC37C935-QS Datasheet - Page 25

• Manufacturer Part Number: FDC37C935-QS
• Manufacturer: Standard Microsystems (SMSC)

Specifications of FDC37C935-QS

• Lead Free Status / RoHS Status: Supplier Unconfirmed

DATA REGISTER (FIFO)
Address 3F5 READ/WRITE
All command parameter information, disk data
and result status are transferred between the
host processor and the floppy disk controller
through the Data Register. Data transfers are
governed by the RQM and DIO bits in the Main
Status Register.
The Data Register defaults to FIFO disabled
mode after any form of reset. This maintains
PC/AT hardware compatibility.
values can be changed through the Configure
command (enable full FIFO operation with
threshold control). The advantage of the FIFO
is that it allows the system
latency without causing a disk error. Table 14
gives several examples of the delays with a
FIFO THRESHOLD
FIFO THRESHOLD
FIFO THRESHOLD
EXAMPLES
EXAMPLES
EXAMPLES
*The 2 Mbps data rate is only available if V
15 bytes
15 bytes
15 bytes
2 bytes
8 bytes
2 bytes
8 bytes
2 bytes
8 bytes
1 byte
1 byte
1 byte
a larger DMA
Table 14 - FIFO Service Delay
The default
1 x 4 s - 1.5 s = 2.5 s
2 x 4 s - 1.5 s = 6.5 s
8 x 4 s - 1.5 s = 30.5 s
15 x 4 s - 1.5 s = 58.5 s
1 x 8 s - 1.5 s = 6.5 s
2 x 8 s - 1.5 s = 14.5 s
8 x 8 s - 1.5 s = 62.5 s
15 x 8 s - 1.5 s = 118.5 s
1 x 16 s - 1.5 s = 14.5 s
2 x 16 s - 1.5 s = 30.5 s
8 x 16 s - 1.5 s = 126.5 s
15 x 16 s - 1.5 s = 238.5 s
MAXIMUM DELAY TO SERVICING
MAXIMUM DELAY TO SERVICING
MAXIMUM DELAY TO SERVICING
25
AT 500 Kbps DATA RATE
AT 2 Mbps* DATA RATE
AT 1 Mbps DATA RATE
formula:
At the start of a command, the FIFO action is
always disabled and command parameters
must be sent based upon the RQM and DIO bit
settings. As the command execution phase is
entered, the FIFO is cleared of any data to
ensure that invalid data is not transferred.
An overrun or underrun will terminate the
current command and the transfer of data. Disk
writes will complete the current sector by
generating a 00 pattern and valid CRC. Reads
require the host to remove the remaining data
so that the result phase may be entered.
Threshold # x
CC
DATA RATE
= 5V.
1 x 8
-1.5 s = DELAY
u