ISP1181BDGG,112 STEricsson, ISP1181BDGG,112 Datasheet - Page 16

• Manufacturer Part Number: ISP1181BDGG,112
• Manufacturer: STEricsson

Specifications of ISP1181BDGG,112

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

10. DMA transfer
ISP1181B_3
Product data sheet
10.1 Selecting an endpoint for DMA transfer
Direct Memory Access (DMA) is a method to transfer data from one location to another in
a computer system, without intervention of the central processor (CPU). Many different
implementations of DMA exist. The ISP1181B supports two methods:
The ISP1181B supports DMA transfer for all 14 configurable endpoints (see
one endpoint at a time can be selected for DMA transfer. The DMA operation of the
ISP1181B can be interleaved with normal I/O mode access to other endpoints.
The following features are supported:
The target endpoint for DMA access is selected via bits EPDIX[3:0] in the DMA
Configuration Register, as shown in
automatically set by bit EPDIR in the associated ECR, to match the selected endpoint
type (OUT endpoint: read; IN endpoint: write).
Asserting input DACK automatically selects the endpoint specified in the DMA
Configuration Register, regardless of the current endpoint used for I/O mode access.
Table 7.
•
•
•
•
•
•
8237 compatible mode: based on the DMA subsystem of the IBM personal
computers (PC, AT and all its successors and clones); this architecture uses the Intel
8237 DMA controller and has separate address spaces for memory and I/O
DACK-only mode: based on the DMA implementation in some embedded RISC
processors, which has a single address space for both memory and I/O.
Single-cycle or burst transfers (up to 16 bytes per cycle)
Programmable transfer direction (read or write)
Multiple End-Of-Transfer (EOT) sources: external pin, internal conditions, short/empty
packet
Programmable signal levels on pins DREQ, DACK and EOT.
Endpoint
identifier
10
11
1
2
3
4
5
6
7
8
9
Endpoint selection for DMA transfer
Rev. 03 — 23 January 2009
EPIDX[3:0]
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
Table
7. The transfer direction (read or write) is
EPDIR = 0
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
OUT: read
Full-speed USB peripheral controller
Transfer direction
© ST-NXP Wireless 2009. All rights reserved.
ISP1181B
EPDIR = 1
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
IN: write
Table
4). Only
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