ISP1181BDGG,112 STEricsson, ISP1181BDGG,112 Datasheet - Page 32

• Manufacturer Part Number: ISP1181BDGG,112
• Manufacturer: STEricsson

Specifications of ISP1181BDGG,112

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 26.
ISP1181B_3
Product data sheet
Bit
Symbol
Reset
Access
Bit
Symbol
Reset
Access
DMA Counter Register: bit allocation
12.1.7 Write/Read DMA Counter
12.1.8 Reset Device
R/W
R/W
15
0
7
0
Table 25.
This command accesses the DMA Counter Register, which consists of 2 bytes. The bit
allocation is given in
transfer. Reading the register returns the number of remaining bytes in the current
transfer. A bus reset will not change the programmed bit values.
The internal DMA counter is automatically reloaded from the DMA Counter Register when
DMA is re-enabled (DMAEN = 1). See
Code (Hex): F2/F3 — write/read DMA Counter Register
Transaction — write/read 2 bytes
Table 27.
This command resets the ISP1181B in the same way as an external hardware reset via
input RESET. All registers are initialized to their ‘reset’ values.
Code (Hex): F6 — reset the device
Transaction — none
Bit
3
2
1 to 0
Bit
15 to 8
7 to 0
R/W
R/W
14
0
6
0
DMA Configuration Register: bit description
DMA Counter Register: bit description
Symbol
DMAEN
-
BURSTL[1:0]
Symbol
DMACRH[7:0]
DMACRL[7:0]
R/W
R/W
13
0
5
0
Table
Rev. 03 — 23 January 2009
26. Writing to the register sets the number of bytes for a DMA
Description
Writing a logic 1 enables DMA transfer, a logic 0 forces the end of
an ongoing DMA transfer. Reading this bit indicates whether DMA is
enabled (0 = DMA stopped, 1 = DMA enabled). This bit is cleared
by a bus reset.
reserved
Selects the DMA burst length:
00 — single-cycle mode (1 byte)
01 — burst mode (4 bytes)
10 — burst mode (8 bytes)
11 — burst mode (16 bytes).
Bus reset value: unchanged.
Description
DMA Counter Register (high byte)
DMA Counter Register (low byte)
R/W
R/W
12
0
4
0
DMACRH[7:0]
DMACRL[7:0]
Section 12.1.6
R/W
R/W
11
0
3
0
Full-speed USB peripheral controller
…continued
for more details.
R/W
R/W
10
0
2
0
© ST-NXP Wireless 2009. All rights reserved.
R/W
R/W
ISP1181B
9
0
1
0
R/W
R/W
8
0
0
0
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