ISP1181BDGG,112 STEricsson, ISP1181BDGG,112 Datasheet - Page 69

• Manufacturer Part Number: ISP1181BDGG,112
• Manufacturer: STEricsson

Specifications of ISP1181BDGG,112

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

26. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. Summary of EOT conditions for a bulk
Table 11. Recommended EOT usage for isochronous
Table 12. Summary of control bits . . . . . . . . . . . . . . . . . .22
Table 13. Command and register summary . . . . . . . . . .23
Table 14. Endpoint Configuration Register: bit allocation 26
Table 15. Endpoint Configuration Register: bit
Table 16. Address Register: bit allocation . . . . . . . . . . . .26
Table 17. Address Register: bit description . . . . . . . . . . .26
Table 18. Mode Register: bit allocation . . . . . . . . . . . . . .27
Table 19. Mode Register: bit description . . . . . . . . . . . . .27
Table 20. Hardware Configuration Register: bit
Table 21. Hardware Configuration Register: bit
Table 22. Interrupt Enable Register: bit allocation . . . . . .29
Table 23. Interrupt Enable Register: bit description . . . . .29
Table 24. DMA Configuration Register: bit allocation . . .30
Table 25. DMA Configuration Register: bit description . .30
Table 26. DMA Counter Register: bit allocation . . . . . . . .31
Table 27. DMA Counter Register: bit description . . . . . .31
Table 28. Endpoint FIFO organization . . . . . . . . . . . . . . .32
Table 29. Example of endpoint FIFO access (8-bit bus
Table 30. Example of endpoint FIFO access (16-bit bus
Table 31. Endpoint Status Register: bit allocation . . . . . .33
Table 32. Endpoint Status Register: bit description . . . .34
Table 33. Endpoint Status Image Register: bit allocation 35
Table 34. Endpoint Status Image Register: bit
Table 35. Error Code Register: bit allocation . . . . . . . . . .36
Table 36. Error Code Register: bit description . . . . . . . .36
Table 37. Transaction error codes . . . . . . . . . . . . . . . . . .36
Table 38. Lock Register: bit allocation . . . . . . . . . . . . . . .37
Table 39. Lock Register: bit description . . . . . . . . . . . . .37
Table 40. Scratch Information Register: bit allocation . . .38
Table 41. Scratch Information Register: bit description . .38
Table 42. Frame Number Register: bit allocation . . . . . .38
Table 43. Frame Number Register: bit description . . . . .38
Table 44. Example of Frame Number Register access (8-bit
Table 45. Example of Frame Number Register access
Table 46. Chip ID Register: bit allocation . . . . . . . . . . . .39
ISP1181B_3
Product data sheet
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
Bus configuration modes . . . . . . . . . . . . . . . . . 11
Endpoint access and programmability . . . . . . .12
Programmable FIFO size . . . . . . . . . . . . . . . . .13
Memory configuration example . . . . . . . . . . . .13
Endpoint selection for DMA transfer . . . . . . . .15
8237 compatible mode: pin functions . . . . . . .16
DACK-only mode: pin functions . . . . . . . . . . . .17
endpoint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
endpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
width) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33
description . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
bus width) . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
(16-bit bus width) . . . . . . . . . . . . . . . . . . . . . . .39
Rev. 03 — 23 January 2009
Table 47. Chip ID Register: bit description . . . . . . . . . . . 39
Table 48. Interrupt Register: bit allocation . . . . . . . . . . . 40
Table 49. Interrupt Register: bit description . . . . . . . . . . 40
Table 50. Absolute maximum ratings . . . . . . . . . . . . . . . 45
Table 51. Recommended operating conditions . . . . . . . 45
Table 52. Static characteristics; supply pins . . . . . . . . . . 46
Table 53. Static characteristics: digital pins . . . . . . . . . . 46
Table 54. Static characteristics: analog I/O pins
Table 55. Dynamic characteristics . . . . . . . . . . . . . . . . . 48
Table 56. Dynamic characteristics: analog I/O pins
Table 57. Dynamic characteristics: parallel interface
Table 58. Dynamic characteristics: access cycle timing . 52
Table 59. Dynamic characteristics: single-cycle DMA
Table 60. Dynamic characteristics: burst mode DMA
Table 61. SnPb eutectic process (from J-STD-020C) . . . 65
Table 62. Lead-free process (from J-STD-020C) . . . . . . 65
Table 63. Revision history . . . . . . . . . . . . . . . . . . . . . . . . 67
(D+, D )
(D+, D )
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Full-speed USB peripheral controller
[1]
[1]
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
. . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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ISP1181B
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