ISP1181BDGG,112 STEricsson, ISP1181BDGG,112 Datasheet - Page 37

• Manufacturer Part Number: ISP1181BDGG,112
• Manufacturer: STEricsson

Specifications of ISP1181BDGG,112

• Operating Temperature (max): 85C
• Operating Temperature (min): -40C
• Operating Temperature Classification: Industrial
• Package Type: TSSOP
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Supplier Unconfirmed

Table 35.
ISP1181B_3
Product data sheet
Bit
Symbol
Reset
Access
Error Code Register: bit allocation
12.2.7 Acknowledge Setup
12.3.1 Read Endpoint Error Code
UNREAD
12.3 General commands
R
7
0
This command acknowledges to the host that a SETUP packet was received. The arrival
of a SETUP packet disables the Validate Buffer and Clear Buffer commands for the
control IN and OUT endpoints. The microcontroller needs to re-enable these commands
by sending an Acknowledge Setup command, see
Code (Hex): F4 — acknowledge setup
Transaction — none
This command returns the status of the last transaction of the selected endpoint, as stored
in the Error Code Register. Each new transaction overwrites the previous status
information. The bit allocation of the Error Code Register is shown in
Code (Hex): A0 to AF — read error code (control OUT, control IN, endpoint 1 to 14)
Transaction — read 1 byte
Table 36.
Table 37.
Bit
7
6
5
4 to 1
0
Error code
(Binary)
0000
0001
0010
0011
0100
0101
0110
DATA01
R
6
0
Transaction error codes
Error Code Register: bit description
Symbol
UNREAD
DATA01
-
ERROR[3:0]
RTOK
Description
no error
PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0
PID unknown; encoding is valid, but PID does not exist
unexpected packet; packet is not of the expected type (token, data, or
acknowledge), or is a SETUP token to a non-control endpoint
token CRC error
data CRC error
time-out error
reserved
R
5
0
Rev. 03 — 23 January 2009
Description
A logic 1 indicates that a new event occurred before the previous
status was read.
This bit indicates the PID type of the last successfully received or
transmitted packet (0 = DATA0 PID, 1 = DATA1 PID).
reserved
Error code. For error description, see
A logic 1 indicates that data was received or transmitted
successfully.
R
4
0
R
3
0
ERROR[3:0]
Full-speed USB peripheral controller
Section
R
2
0
9.5.
Table
© ST-NXP Wireless 2009. All rights reserved.
37.
ISP1181B
Table
R
1
0
35.
RTOK
R
0
0
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