AM53CF96KC/W AMD (ADVANCED MICRO DEVICES), AM53CF96KC/W Datasheet - Page 16

• Manufacturer Part Number: AM53CF96KC/W
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM53CF96KC/W

• Lead Free Status / RoHS Status: Not Compliant

RSTC
Reset Control
(Output, Active Low, Open Drain)
This is a SCSI output with 48 mA drive. The Reset SCSI
command will cause the device to drive RSTC active for
25 ms–40 ms, which will depend on the CLK frequency
and the conversion factor. When the device is config-
ured in the Single Ended SCSI Mode (DFMODE inac-
tive) this pin is defined as a RST output for the SCSI bus.
When the device is configured in the Differential SCSI
Mode (DFMODE active) this pin is defined as the direc-
tion control for the external differential transceiver. In
this mode, a signal high state corresponds to an output
to the SCSI bus and a low state corresponds to an input
from the SCSI bus.
REQC
Request Control
(Output, Active Low, Open Drain)
This is a SCSI output with 48 mA drive. This signal is
activated only in the Target mode.
FUNCTIONAL DESCRIPTION
Register Map
16
Address
Note:
Not all registers in this device are both readable and writable. Some read only registers share the same address with write only
registers. The registers can be accessed by asserting the CS signal and then asserting either RD or WR signal depending on the
operation to be performed. Only the FIFO Register can be accessed by asserting either CS or DACK in conjunction with RD and
WR signals or DMARD and DMAWR signals. The register address inputs are ignored when DACK is used but must be valid
when CS is used.
(Hex.)
00
00
01
01
02
03
04
04
05
05
06
06
AMD
Read/Write
Read/Write
Operation
Read
Write
Read
Write
Read
Write
Read
Write
Read
Write
Register
Current Transfer Count
Register Low
Start Transfer Count Register
Low
Current Transfer Count
Register Middle
Start Transfer Count Register
Middle
FIFO Register
Command Register
Status Register
SCSI Destination ID Register
Interrupt Status Register
SCSI Timeout Register
Internal State Register
Synchronous Transfer Period
Register
Am53CF94/Am53CF96
Address
(Hex.)
ACKC
Acknowledge Control
(Output, Active Low, Open Drain)
This is a SCSI output with 48 mA drive. This signal is ac-
tivated only in the Initiator mode.
ISEL
Initiator Select
(Output, Active High)
This signal is available on the Am53CF96 only. This sig-
nal is active whenever the device is in the Initiator mode.
In the differential mode this signal is used to enable the
Initiator signals ACKC and ATN and the device also
drives these signals.
TSEL
Target Select
(Output, Active High)
This signal is available on the Am53CF96 only. This sig-
nal is active whenever the device is in the Target mode.
In the differential mode this signal is used to enable the
Target signals REQC, MSG, C/D and I/O and the device
also drives these signals.
0C
0D
0A
0B
0E
0E
0F
07
07
08
09
Read/Write
Read/Write
Read/Write
Read/Write
Operation
Write
Read
Write
Write
Write
Read
Write
Register
Current FIFO/Internal State
Register
Synchronous Offset Register
Control Register 1
Clock Factor Register
Forced Test Mode Register
Control Register 2
Control Register 3
Control Register 4
Current Transfer Count
Register High
Start Transfer Count
Register High
Data Alignment Register