MC33580BAPNA Freescale, MC33580BAPNA Datasheet - Page 22

• Manufacturer Part Number: MC33580BAPNA
• Manufacturer: Freescale

Specifications of MC33580BAPNA

• Switch Type: High Side
• Power Switch Family: MC33580
• Input Voltage: 6 to 27V
• Power Switch On Resistance: 30mOhm
• Number Of Outputs: 4
• Mounting: Surface Mount
• Supply Current: 20mA
• Package Type: Power QFN
• Operating Temperature (min): -40C
• Operating Temperature Classification: Automotive
• Pin Count: 24
• Lead Free Status / RoHS Status: Compliant

SERIAL INPUT COMMUNICATION
messages. A message is transmitted by the MCU starting
with the MSB D15 and ending with the LSB, D0
Each incoming command message on the SI pin can be
interpreted using the following bit assignments: the MSB,
D15, is the watchdog bit. In some cases, output selection is
done with bits D12 : D11. The next three bits, D10 : D8, are
used to select the command register. The remaining five bits,
D4 : D0, are used to configure and control the outputs and
their protection features.
22
33580
Table 8. SI Message Bit Assignment
Table 9. Serial Input Address and Configuration Bit Map
FUNCTIONAL DEVICE OPERATION
LOGIC COMMANDS AND REGISTERS
SI Register
SOCHLR_s WDIN
CDTOLR_s WDIN
x = Don’t care.
s = Output selection with the bits A
D15 is used to toggle watchdog event (WDIN).
STATR_s
DICR_s
SPI communication is accomplished using 16-bit
RESET
UOVR
OCR0
OCR1
WDR
NAR
Bit Sig
MSB
LSB
WDIN
WDIN
WDIN
WDIN
WDIN
WDIN
WDIN
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5
0
0
0
0
0
0
0
0
0
0
0
SI Msg Bit
D14
D12
D10
D7
D4
0
0
0
0
0
0
0
0
0
0
D15
D0
:
:
:
:
:
D15
D11
D5
D1
D8
A
A
A
X
0
0
0
0
0
0
1
1
1
1
A
0
A
A
A
0
0
1
0
1
0
X
as defined in
0
0
0
LOGIC COMMANDS AND REGISTERS
0
0
0
0
0
1
1
1
1
X
Watchdog in: toggled to satisfy watchdog requirements.
Not used.
Register address bits used in some cases for output selection.
Register address bits.
Not used.
Used to configure the inputs, outputs, and the device protection features and SO status content.
Used to configure the inputs, outputs, and the device protection features and SO status content.
X
0
0
0
1
1
0
0
0
1
Table
(Table
X
0
1
1
0
1
0
1
1
0
10.
8).
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
SI Data
accommodate those applications where daisy-chaining is
desirable, or to confirm transmitted data, as long as the
messages are all multiples of 16 bits. Any attempt made to
latch in a message that is not 16 bits will be ignored.
configure the device and to control the state of the outputs.
Table
SOA4
D4
Multiple messages can be transmitted in succession to
The 33580 has defined registers, which are used to
0
0
0
0
0
0
0
0
0
Message Bit Description
9, page 22, summarizes the SI registers.
FAST_SR_s
OT_latch_3
OT_latch-1
CSNS3
OL_DIS_s
SOCH_s
IN3_SPI
SOA3
D3
0
No Action (Allow Toggling of D15
EN
Analog Integrated Circuit Device Data
CSNS_high_s DIR_DIS_s
OCL_DIS_s
OT_latch_0
OT_latch_2
CSNS2
SOCL2_s
IN2_SPI
SOA2
D2
0
EN
Freescale Semiconductor
CSNS1
SOCL1_s
OCLT1_s
IN1_SPI
UV_DIS
SOA1
WD1
D1
0
EN
-
WDIN)
CSNS0
SOCL0_s
OCLT0_s
IN0_SPI
OV_DIS
A/O_s
SOA0
WD0
D0
0
EN