SPEAR09H042 STMicroelectronics, SPEAR09H042 Datasheet
![no-image](/images/manufacturer_photos/0/6/637/stmicroelectronics_sml.jpg)
SPEAR09H042
Specifications of SPEAR09H042
Related parts for SPEAR09H042
SPEAR09H042 Summary of contents
Page 1
... I C master mode, fast and slow speed ■ 6 general purpose I/Os Table 1. Device summary Order code SPEAR-09-H042 January 2008 For further information contact your local STMicroelectronics sales office. SPEAR-09-H042 ■ Real time clock ■ WatchDog ■ 4 general purpose timers ■ Operating temperature °C ■ ...
Page 2
Contents Contents 1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
Page 3
SPEAR-09-H042 1 Introduction This data brief describes the differences between SPEAr Head200 (SPEAR-09-H022) and the one packaged in LFBGA289 balls 0.8mm pitch (SPEAR-09-H042). In this document the main package characteristics are described as well as the chip features modifications. The ...
Page 4
Features modification 2 Features modification To fit the new small package a number of features has been reduced or limited: ● Analog to digital converter (ADC) ● eASIC GPIOs ● External FPGA emulation mode ● Dynamic RAM data path ● ...
Page 5
SPEAR-09-H042 3 Pin description Table 2 shows the component signals, grouped by function, and the relative ballout diagram. 3.1 Interface signals Table 2. Interface signals Group Debug eASIC eASICGP_IO[00] eASICGP_IO[01] eASICGP_IO[02] eASICGP_IO[03] eASICGP_IO[04] eASICGP_IO[05] eASICGP_IO[06] eASICGP_IO[07] eASICGP_IO[08] eASICGP_IO[09] eASICGP_IO[10] eASICGP_IO[11] ...
Page 6
Pin description Table 2. Interface signals (continued) Group eASICGP_IO[22] eASICGP_IO[23] eASICGP_IO[24] eASICGP_IO[25] eASICGP_IO[26] eASICGP_IO[27] eASICGP_IO[28] eASICGP_IO[29] eASICGP_IO[30] eASICGP_IO[31] eASICGP_IO[32] eASICGP_IO[33] eASICGP_IO[34] eASICGP_IO[35] eASICGP_IO[36] eASICGP_IO[37] eASICGP_IO[38] eASICGP_IO[39] eASICGP_IO[40] eASICGP_IO[41] eASICGP_IO[42] eASICGP_IO[43] eASICGP_IO[44] eASICGP_IO[45] eASICGP_IO[46] eASICGP_IO[47] eASICGP_IO[48] eASICGP_IO[49] eASICGP_IO[50] eASICGP_IO[51] eASICGP_IO[52] eASICGP_IO[53] ...
Page 7
SPEAR-09-H042 Table 2. Interface signals (continued) Group eASICGP_IO[57] eASICGP_IO[58] eASICGP_IO[59] eASICGP_IO[60] eASICGP_IO[61] eASICGP_IO[62] eASICGP_IO[63] eASICGP_IO[64] eASICGP_IO[65] eASICGP_IO[66] eASICGP_IO[67] eASICGP_IO[68] eASICGP_IO[69] eASICGP_IO[70] eASICGP_IO[71] eASICGP_IO[72] eASICGP_IO[73-74] eASICGP_IO[75-76] eASICGP_IO[77-78] eASICGP_IO[79-80] eASICGP_IO[81-82] eASICGP_IO[83-84] eASICGP_IO[85-86] eASICGP_IO[87-88] eASICGP_IO[89-90] eASICGP_IO[91-92] eASICGP_IO[93-94] eASICGP_IO[95-96] eASICGP_IO[97-98] eASICGP_IO[99] eASIC_EXT_CLOCK eASIC_PI_CLOCK Ethernet ...
Page 8
Pin description Table 2. Interface signals (continued) Group GPI/Os I2C JTAG Master clock Master reset MPMC MPMCDATA[00] MPMCDATA[01] MPMCDATA[02] MPMCDATA[03] 8/16 Signal Name Ball Direction TXD[2] D15 Output TXD[3] D16 TX_EN D17 CRS E15 Input COL E16 RX_CLK E17 Input ...
Page 9
SPEAR-09-H042 Table 2. Interface signals (continued) Group MPMCDATA[04] MPMCDATA[05] MPMCDATA[06] MPMCDATA[07] MPMCDATA[08] MPMCDATA[09] MPMCDATA[10] MPMCDATA[11] MPMCDATA[12] MPMCDATA[13] MPMCDATA[14] MPMCDATA[15] MPMCADDROUT[00] MPMCADDROUT[01] MPMCADDROUT[02] MPMCADDROUT[03] MPMCADDROUT[04] MPMCADDROUT[05] MPMCADDROUT[06] MPMCADDROUT[07] MPMCADDROUT[08] MPMCADDROUT[09] MPMCADDROUT[10] MPMCADDROUT[11] MPMCADDROUT[12] MPMCADDROUT[13] MPMCADDROUT[14] nMPMCDYCSOUT[0] nMPMCDYCSOUT[1] nMPMCDYCSOUT[2] nMPMCDYCSOUT[3] MPMCCKEOUT[0] MPMCCKEOUT[1] ...
Page 10
Pin description Table 2. Interface signals (continued) Group MPMCCLKOUT[1] nMPMCCLKOUT[1] MPMCDQMOUT[0] MPMCDQMOUT[1] nMPMCCASOUT nMPMCRASOUT nMPMCWEOUT RTC SMI UART USBs HOST1_VBUS HOST2_VBUS 10/16 Signal Name Ball Direction U14 U13 T16 Output U17 MPMCDQS[0] R16 Output MPMCDQS[1] R17 T6 Output U6 U5 ...
Page 11
SPEAR-09-H042 3.2 Power connections Table 3. Power connections Group vdd1v2_date_osci gnd_date_osci gnde_date_osci anavdd_3v3_pll1600 anagnd_3v3_pll1600 digvdd_1v2_pll1600 diggnd_1v2_pll1600 Power Signal Name Ball (1) vdd3v3 Digital 3.3V power (2) vdd Digital 1.2V power (3) gnd Digital ground vdd_dith P6 DDR / SDR dedicated ...
Page 12
Pin description Table 3. Power connections (continued) Group 1. Signal spread on the following balls: H11, J08, J09, J13, J14, K14, M14, N14, P14. 2. Signal spread on the following balls: H10, J07, J12, L14, N05, P09, P13. 3. Signal ...
Page 13
SPEAR-09-H042 3.3 Ballout top view Figure 1. Ballout top view SIC G eA SIC G eA SIC G eA SIC G eA SIC _IO _IO _IO[ 22 ...
Page 14
Package information 4 Package information In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the ...
Page 15
SPEAR-09-H042 5 Revision history Table 4. Document revision history Date 31-Jan-2008 Revision 1 Initial release. Revision history Changes 15/16 ...
Page 16
... Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST’s terms and conditions of sale. ...