SPEAR09H042 STMicroelectronics, SPEAR09H042 Datasheet - Page 13

• Manufacturer Part Number: SPEAR09H042
• Manufacturer: STMicroelectronics

Specifications of SPEAR09H042

• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Package Type: LFBGA
• Pin Count: 289
• Mounting: Surface Mount
• Rad Hardened: No
• Lead Free Status / RoHS Status: Supplier Unconfirmed

SPEAR-09-H042
3.3
Figure 1.
M
A
C
G
B
D
E
F
H
J
K
L
N
P
R
T
U
eA SIC G
eA SIC G
eA SIC G
eA SIC G
OVER C
H OST1_
H OST1_
M C LK_i
vddc_1v
dat e_o s
P _IO[ 21
P _IO[ 17
P _IO[ 14
P _IO[ 10
YP A SS
vssl_3v
H OST2
vssl_3v
vdd1v2_
gnde_u
P LL_B
R TC XI R TC XO
D P LS
UR H 1
VB US
3_h0
_D P
3_h1
2_d
D P
sb
1
ci
1
n
]
]
]
]
eA SIC G
P _IO[ 33
eA SIC G
P _IO[ 30
eA SIC G
P _IO[ 24
eA SIC G
OVER C
H OST1_
vddb_1v
at e_o sc
P _IO[ 7]
H OST2
H OST2
M C LK_
_VB US
vdd3_3
vdd3_3
vdde3v
D M N S
gnde_d
UR H 2
VB US
v3_h0
3_usb
_D M
v3_h1
D M
2_d
o ut
Ballout top view
Ballout top view
2
2
]
]
]
i
eA SIC G
P _IO[ 22
eA SIC G
P _IO[ 32
eA SIC G
P _IO[ 26
eA SIC G
eA SIC G
eA SIC G
M R ESE
vssc_1v
vddb_1v
_3v3_pll
vssc_1v
gnd_dat
vdd_dat
P _IO[ 9]
P _IO[ 8]
P _IO[ 4]
digvdd_
vddl_1v
vddl_1v
anavdd
1v2_pll1
vdd3_3
e_o sci
e_o sci
2_h0
2_h0
v3_d
2_h1
2_h1
1600
2_d
600
3
T
3
]
]
]
eA SIC G
P _IO[ 23
eA SIC G
eA SIC G
P _IO[ 34
eA SIC G
eA SIC G
eA SIC G
P _IO[ 25
eA SIC G
vssb_1v
vddb_1v
vssb_1v
vddc_1v
_3v3_pll
vssb_1v
C D YC S
C D YC S
P _IO[ 19
P _IO[ 13
P _IO[ 5]
P _IO[ 0]
diggnd_
vssl_3v
anagnd
1v2_pll1
nM P M
nM P M
OUT[ 0]
OUT[ 1]
2_h0
2_h0
2_h1
2_h1
1600
2_d
600
3_d
4
4
]
]
]
]
]
eA SIC G
P _IO[ 35
eA SIC G
P _IO[ 28
eA SIC G
P _IO[ 27
eA SIC G
P _IO[ 40
eA SIC G
eA SIC G
eA SIC G
eA SIC G
vddc_1v
vssc_1v
C D YC S
C D YC S
C WEOU
P _IO[ 15
P _IO[ 6]
P _IO[ 31
P _IO[ 3]
gnd_us
vdd_us
vddl_1v
nM P M
OUT[ 3]
nM P M
OUT[ 2]
nM P M
2_h0
2_h1
vdd
2_d
5
T
5
b
b
]
]
]
]
]
]
eA SIC G
P _IO[ 42
eA SIC G
eA SIC G
P _IO[ 37
eA SIC G
P _IO[ 54
eA SIC G
eA SIC G
eA SIC G
eA SIC G
C C A SO
C R A SO
P _IO[ 41
P _IO[ 18
P _IO[ 16
P _IO[ 11
P _IO[ 2]
M P M C
vdd2v5 vdd2v5
vdd_dit
OUT[ 0]
nM P M
nM P M
A D D R
R R EF
gnd
gnd
gnd
UT
UT
6
6
h
]
]
]
]
]
]
eA SIC G
P _IO[ 50
eA SIC G
P _IO[ 47
eA SIC G
P _IO[ 39
eA SIC G
P _IO[ 56
eA SIC G
P _IO[ 48
eA SIC G
P _IO[ 20
eA SIC G
eA SIC G
P _IO[ 12
M P M C
M P M C
M P M C
P _IO[ 1]
vss_dit
OUT[ 3]
OUT[ 2]
A D D R
A D D R
A D D R
OUT[ 1]
vdd
gnd
gnd
gnd
7
7
h
]
]
]
]
]
]
]
eA SIC G
P _IO[ 52
eA SIC G
eA SIC G
P _IO[ 62
eA SIC G
P _IO[ 46
eA SIC G
P _IO[ 44
eA SIC G
P _IO[ 49
eA SIC G
P _IO[ 43
eA SIC G
P _IO[ 29
P _IO[ 51
M P M C
M P M C
M P M C
vdd3v3 vdd3v3
vdd2v5
OUT[ 6]
OUT[ 5]
OUT[ 4]
A D D R
A D D R
A D D R
gnd
gnd
gnd
gnd
8
8
]
]
]
]
]
]
]
]
eA SIC G
P _IO[ 60
eA SIC G
P _IO[ 59
eA SIC G
P _IO[ 58
eA SIC G
P _IO[ 53
eA SIC G
P _IO[ 45
eA SIC G
P _IO[ 55
eA SIC G
P _IO[ 38
eA SIC G
P _IO[ 36
M P M C
M P M C
M P M C
OUT[ 9]
OUT[ 8]
OUT[ 7]
A D D R
A D D R
A D D R
gnd
gnd
gnd
gnd
vdd
9
9
]
]
]
]
]
]
]
]
eA SIC G
P _IO[ 67
eA SIC G
P _IO[ 66
eA SIC G
P _IO[ 65
eA SIC G
P _IO[ 64
eA SIC G
P _IO[ 63
eA SIC G
P _IO[ 57
eA SIC G
OUT[ 12]
OUT[ 10]
P _IO[ 61
M P M C
M P M C
M P M C
vdd2v5 vdd2v5 vdd2v5
OUT[ 11
A D D R
A D D R
A D D R
vdd
gnd
gnd
gnd
gnd
gnd
10
10
]
]
]
]
]
]
]
eA SIC G
P _IO[ 75
eA SIC G
P _IO[ 73
eA SIC G
P _IO[ 72
eA SIC G
eA SIC G
P _IO[ 70
eA SIC G
P _IO[ 69
eA SIC G
P _IO[ 68
OUT[ 14]
OUT[ 13]
P _IO[ 71
M P M C
M P M C
M P M C
C KEOU
vdd3v3 TEST3
A D D R
A D D R
gnd
gnd
gnd
gnd
gnd
T[ 0]
11
11
]
]
]
]
]
]
]
eA SIC G
P _IO[ 77
eA SIC G
P _IO[ 79
eA SIC G
eA SIC G
P _IO[ 83
eA SIC G
P _IO[ 85
D A TA [ 1
P _IO[ 81
M P M C
M P M C
M P M C
C KEOU
D A TA [
R TC K
TD O
vdd
gnd
gnd
gnd
gnd
T[ 1]
12
12
0]
]
]
]
]
]
]
eA SIC G
P _IO[ 87
eA SIC G
P _IO[ 89
eA SIC G
eA SIC G
P _IO[ 93
eA SIC G
P _IO[ 95
P _IO[ 91
M P M C
M P M C
C C LKO
TEST2
vdd3v3 vdd3v3
D A TA [
D A TA [
nM P M
TC K
UT[ 1]
TD I
gnd
gnd
gnd
gnd
vdd
13
13
3]
2]
]
]
]
]
]
eA SIC G
P _IO[ 97
eA SIC G
P _IO[ 99
TA OUT
eA SIC _
M P M C
M P M C
M P M C
TEST0
SM ID A
EXT_C
nTR ST R XD [ 3] R X_D V R X_ER
vdd3v3
vdd3v3
vdd3v3
vdd3v3
D A TA [
D A TA [
C LKOU
TEST1
LOC K
TM S
vdd
T[ 1]
14
14
5]
4]
]
]
P I_C LO
D A TA [ 1
SSTL_V
SM IN C
SM IN C
R XD [ 0] R XD [ 1] R XD [ 2]
eA SIC _
GP _IO[
GP _IO[
M P M C
M P M C
M P M C
C C LKO
TX_C L
TXD [ 2] TXD [ 3] TX_EN
D A TA [
D A TA [
nM P M
M D C
UT[ 0]
C R S
S[ 3]
S[ 0]
SC L
R EF
C K
15
15
3]
0]
7]
6]
K
1]
Pin description
UA R T1_
D A TA [ 1
D A TA [ 1
SM IN C
GP _IO[
GP _IO[
M P M C
M P M C
M P M C
M P M C
M P M C
M P M C
SM IC L
TXD [ 0] TXD [ 1]
D A TA [
D QS[ 0]
D QM O
C LKOU
M D IO
UT[ 0]
C OL
S[ 2]
TXD
T[ 0]
16
16
5]
2]
4]
2]
9]
K
UA R T1_
GP _IO[ 1
D A TA [ 1
D A TA [ 1
D A TA [ 1
SM IN C
SM ID A
GP _IO[
M P M C
M P M C
M P M C
M P M C
M P M C
M P M C
R X_C L
D A TA [
D QM O
D QS[ 1]
TA IN
SD A
R XD
UT[ 1]
S[ 1]
17
17
4]
5]
3]
0]
8]
K
]
13/16
M
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