DSP56321VF275 Freescale, DSP56321VF275 Datasheet - Page 12

• Manufacturer Part Number: DSP56321VF275
• Manufacturer: Freescale

Specifications of DSP56321VF275

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 275MHz
• Mips: 275
• Device Input Clock Speed: 275MHz
• Ram Size: 576KB
• Operating Supply Voltage (typ): 1.6/3.3V
• Operating Supply Voltage (min): 1.5/3/3/3/3/3/3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Signals/Connections
1.5 Interrupt and Mode Control
The interrupt and mode control signals select the chip operating mode as it comes out of hardware reset. After
RESET is deasserted, these inputs are hardware interrupt request lines.
1-6
MODA
IRQA
MODB
IRQB
MODC
IRQC
MODD
IRQD
RESET
PINIT
NMI
Signal Name
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
Type
Schmitt-trigger
Input
Schmitt-trigger
Input
Schmitt-trigger
Input
Schmitt-trigger
Input
Schmitt-trigger
Input
Schmitt-trigger
Input
State During
Table 1-8.
Reset
DSP56321 Technical Data, Rev. 11
Interrupt and Mode Control
Mode Select A—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request A—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the STOP or WAIT
standby state and IRQA is asserted, the processor exits the STOP or WAIT
state.
Mode Select B—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request B—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state
and IRQB is asserted, the processor exits the WAIT state.
Mode Select C—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request C—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state
and IRQC is asserted, the processor exits the WAIT state.
Mode Select D—MODA, MODB, MODC, and MODD select one of 16 initial
chip operating modes, latched into the Operating Mode Register when the
RESET signal is deasserted.
External Interrupt Request D—After reset, this input becomes a level-
sensitive or negative-edge-triggered, maskable interrupt request input during
normal instruction processing. If the processor is in the WAIT standby state
and IRQD is asserted, the processor exits the WAIT state.
Reset—Places the chip in the Reset state and resets the internal phase
generator. The Schmitt-trigger input allows a slowly rising input (such as a
capacitor charging) to reset the chip reliably. When the RESET signal is
deasserted, the initial chip operating mode is latched from the MODA, MODB,
MODC, and MODD inputs. The RESET signal must be asserted after
powerup.
PLL Initial—During assertion of RESET, the value of PINIT determines
whether the DPLL is enabled or disabled.
Nonmaskable Interrupt—After RESET deassertion and during normal
instruction processing, this Schmitt-trigger input is the negative-edge-triggered
NMI request.
Signal Description
Freescale Semiconductor