DSP56321VF275 Freescale, DSP56321VF275 Datasheet - Page 34

• Manufacturer Part Number: DSP56321VF275
• Manufacturer: Freescale

Specifications of DSP56321VF275

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 275MHz
• Mips: 275
• Device Input Clock Speed: 275MHz
• Ram Size: 576KB
• Operating Supply Voltage (typ): 1.6/3.3V
• Operating Supply Voltage (min): 1.5/3/3/3/3/3/3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

Specifications
The asynchronous bus arbitration is enabled by internal synchronization circuits on
synchronization circuits add delay from the external signal until it is exposed to internal logic. As a result of this
delay, a DSP56300 part may assume mastership and assert
reason for timing 250.
Once
DSP56300 components that are potential masters on the same bus. If
is asserted and
Therefore, some non-overlap period between one
ensures that overlaps are avoided.
2.4.6
2-14
No.
317 Read data strobe assertion width
318 Read data strobe deassertion width
319 Read data strobe deassertion width
320 Write data strobe assertion width
321 Write data strobe deassertion width
322 HAS assertion width
BB
HACK assertion width
HACK deassertion width
“Last Data Register” reads
consecutive CVR, ICR, or ISR reads
HACK deassertion width after “Last Data
Register” reads
HACK write deassertion width
•
•
after ICR, CVR and “Last Data Register”
writes
after IVR writes, or
after TXH:TXM:TXL writes (with HLEND=
0), or
after TXL:TXM:TXH writes (with HLEND =
1)
is asserted, there is a synchronization delay from
Host Interface Timing
BB
Characteristic
8,11
is deasserted, another DSP56300 component may assume mastership at the same time.
BG1
BB
BG2
8,11
, or between two
10
Figure 2-12.
5
6
5
5
8
3
after
Table 2-10.
DSP56321 Technical Data, Rev. 11
2.5 × T
2.5 × T
Expression
Asynchronous Bus Arbitration Timing
T
C
BG
+ 4.95
Host Interface Timings
C
C
+ 3.3
+ 3.3
input active to another
BB
Min
9.95
4.95
15.8
15.8
8.25
4.95
BB
250
6.6
200 MHz
assertion to the time this assertion is exposed to other
, for some time after
250+251
Max
—
—
—
—
—
—
—
BG
Min
9.05
14.7
14.7
4.5
6.0
7.5
4.5
220 MHz
input is asserted before that time, and
1,2,12
BG
251
Max
input active is required. Timing 251
—
—
—
—
—
—
—
BG
BG
Min
4.13
13.7
13.7
6.88
4.13
8.3
5.5
240 MHz
is deasserted. This is the
and
Max
Freescale Semiconductor
BB
—
—
—
—
—
—
—
inputs. These
12.39
12.39
Min
7.77
6.28
4.0
5.1
4.0
275 MHz
Max
—
—
—
—
—
—
—
Uni
BG
ns
ns
ns
ns
ns
ns
ns
t