DSP56321VF275 Freescale, DSP56321VF275 Datasheet - Page 17

• Manufacturer Part Number: DSP56321VF275
• Manufacturer: Freescale

Specifications of DSP56321VF275

• Device Core Size: 24b
• Format: Fixed Point
• Clock Freq (max): 275MHz
• Mips: 275
• Device Input Clock Speed: 275MHz
• Ram Size: 576KB
• Operating Supply Voltage (typ): 1.6/3.3V
• Operating Supply Voltage (min): 1.5/3/3/3/3/3/3V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 196
• Package Type: MA-BGA
• Lead Free Status / RoHS Status: Not Compliant

1.8 Enhanced Synchronous Serial Interface 1 (ESSI1)
Freescale Semiconductor
STD0
PC5
Notes:
SC10
PD0
SC11
PD1
SC12
PD2
Signal Name
Signal Name
1.
2.
In the Stop state, the signal maintains the last state as follows:
• If the last state is input, the signal is an ignored input.
• If the last state is output, these lines have weak keepers that maintain the last output state even if the drivers are tri-stated.
The Wait processing state does not affect the signal state.
Output
Input or Output
Input or Output
Input or Output
Input/Output
Input or Output
Input/Output
Input or Output
Type
Type
Table 1-11.
Table 1-12.
State During
State During
Ignored Input
Ignored Input
Ignored Input
Ignored Input
Reset
Reset
Enhanced Synchronous Serial Interface 0 (Continued)
DSP56321 Technical Data, Rev. 11
1,2
1,2
Enhanced Serial Synchronous Interface 1
Serial Transmit Data—Transmits data from the Serial Transmit Shift Register.
STD0 is an output when data is transmitted.
Port C 5—The default configuration following reset is GPIO input PC5. When
configured as PC5, signal direction is controlled through the Port C Direction
Register. The signal can be configured as an ESSI signal STD0 through the Port
C Control Register.
Serial Control 0—For asynchronous mode, this signal is used for the receive
clock I/O (Schmitt-trigger input). For synchronous mode, this signal is used
either for transmitter 1 output or for serial I/O flag 0.
Port D 0—The default configuration following reset is GPIO input PD0. When
configured as PD0, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC10 through the Port
D Control Register.
Serial Control 1—For asynchronous mode, this signal is the receiver frame
sync I/O. For synchronous mode, this signal is used either for Transmitter 2
output or for Serial I/O Flag 1.
Port D 1—The default configuration following reset is GPIO input PD1. When
configured as PD1, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC11 through the Port
D Control Register.
Serial Control Signal 2—The frame sync for both the transmitter and receiver
in synchronous mode and for the transmitter only in asynchronous mode. When
configured as an output, this signal is the internally generated frame sync signal.
When configured as an input, this signal receives an external frame sync signal
for the transmitter (and the receiver in synchronous operation).
Port D 2—The default configuration following reset is GPIO input PD2. When
configured as PD2, signal direction is controlled through the Port D Direction
Register. The signal can be configured as an ESSI signal SC12 through the Port
D Control Register.
Enhanced Synchronous Serial Interface 1 (ESSI1)
Signal Description
Signal Description
1-11