MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 202

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

Chapter 6 XGATE (S12XGATEV2)
6.4
The core of the XGATE module is a RISC processor which is able to access the MCU’s internal memories
and peripherals (see
by an XGATE request. Then it executes a code sequence that is associated with the request and optionally
triggers an interrupt to the S12X_CPU upon completion. Code sequences are not interruptible. A new
XGATE request can only be serviced when the previous sequence is finished and the RISC core becomes
idle.
The XGATE module also provides a set of hardware semaphores which are necessary to ensure data
consistency whenever RAM locations or peripherals are shared with the S12X_CPU.
The following sections describe the components of the XGATE module in further detail.
6.4.1
The RISC core is a 16 bit processor with an instruction set that is well suited for data transfers, bit
manipulations, and simple arithmetic operations (see
It is able to access the MCU’s internal memories and peripherals without blocking these resources from
the S12X_CPU
will be stalled until the resource becomes available again
The XGATE offers a high access rate to the MCU’s internal RAM. Depending on the bus load, the RISC
core can perform up to two RAM accesses per S12X_CPU bus cycle.
Bus accesses to peripheral registers or flash are slower. A transfer rate of one bus access per S12X_CPU
cycle can not be exceeded.
The XGATE module is intended to execute short interrupt service routines that are triggered by peripheral
modules or by software.
6.4.2
1. With the exception of PRR registers (see Section “S12X_MMC”).
202
Functional Description
XGATE RISC Core
Programmer’s Model
1
. Whenever the S12X_CPU and the RISC core access the same resource, the RISC core
Figure
15
15
15
15
15
15
15
15
6-1). The RISC processor always remains in an idle state until it is triggered
Register Block
R7
R0 = 0
R6
R5
R4
R3
R2
R1
MC9S12XDP512 Data Sheet, Rev. 2.21
Figure 6-19. Programmer’s Model
(Variable Pointer)
0
0
0
0
0
0
0
0
Section 6.8, “Instruction
15
1
.
Program Counter
PC
Condition
Register
N Z
3 2
Set”).
Code
V C
1 0
0
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