MC9S12XDT512CAA Freescale, MC9S12XDT512CAA Datasheet - Page 603

• Manufacturer Part Number: MC9S12XDT512CAA
• Manufacturer: Freescale

Specifications of MC9S12XDT512CAA

• Cpu Family: HCS12
• Device Core Size: 16b
• Frequency (max): 40MHz
• Interface Type: CAN/I2C/SCI/SPI
• Total Internal Ram Size: 32KB
• # I/os (max): 59
• Number Of Timers - General Purpose: 12
• Operating Supply Voltage (typ): 2.5/5V
• Operating Supply Voltage (max): 2.75/5.5V
• Operating Supply Voltage (min): 2.35/3.15V
• On-chip Adc: 8-chx10-bit
• Instruction Set Architecture: CISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 80
• Package Type: PQFP
• Program Memory Type: Flash
• Program Memory Size: 512KB
• Lead Free Status / RoHS Status: Compliant

16.3.1.3
Read: Anytime
Write: Anytime
Freescale Semiconductor
Address: 0x0127
INT_CFADDR[7:4]
Reset
W
Field
R
7–4
Interrupt Request Configuration Address Register (INT_CFADDR)
0
7
Interrupt Request Configuration Data Register Select Bits — These bits determine which of the 128
configuration data registers are accessible in the 8 register window at INT_CFDATA0–7. The hexadecimal
value written to this register corresponds to the upper nibble of the lower byte of the interrupt vector, i.e.,
writing 0xE0 to this register selects the configuration data register block for the 8 interrupt vector requests
starting with vector (vector base + 0x00E0) to be accessible as INT_CFDATA0–7.
Note: Writing all 0s selects non-existing configuration registers. In this case write accesses to
Figure 16-5. Interrupt Configuration Address Register (INT_CFADDR)
= Unimplemented or Reserved
INT_CFDATA0–7 will be ignored and read accesses will return all 0.
INT_CFADDR[7:4]
0
6
Table 16-5. INT_CFADDR Field Descriptions
MC9S12XDP512 Data Sheet, Rev. 2.21
0
5
1
4
Description
0
0
3
0
0
2
Chapter 16 Interrupt (S12XINTV1)
0
0
1
0
0
0
603