SAA7113HV2 NXP Semiconductors, SAA7113HV2 Datasheet - Page 26

• Manufacturer Part Number: SAA7113HV2
• Manufacturer: NXP Semiconductors

Specifications of SAA7113HV2

• Video Resolution (max): 720Pixels
• Pin Count: 44
• Package Type: PQFP
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
9397 750 14232
Product data sheet
The data type selections by LCR are overruled by setting VIPB (subaddress 11h, bit 1) to
logic 1. This setting is mainly intended for device production tests. The VPO-bus carries
the upper or lower 8 bits of the two ADCs depending on the ADLSB (subaddress 13h,
bit 7) setting. The output configuration is done via MODE3 to MODE0 settings
(subaddress 02h, bits 3 to 0; see
carries the multiplexed output signals of both ADCs, in CVBS-mode the output of only one
ADC. No timing reference codes are generated in this mode.
Remark: The LSBs (bit 0) of the ADCs are available on pins RTS0 or RTS1.
See
The SAV/EAV timing reference codes define start and end of valid data regions.
Table 8:
The generation of the H-bit and consequently the timing of SAV/EAV corresponds to the
selected data format. H = 0 during active data region. For all data formats excluding data
type 7 (raw data), the length of the active data region is 1440 LLC. For the YUV 4 : 2 : 2
formats (data types 15 and 6) every clock cycle within this range contains valid data
(see
The sliced data stream (various standards, data types 0 to 5 and 8 to 14; see
contains also invalid cycles marked as 00h.
The length of the raw data region (data type 7) is programmable via HSB7 to HSB0 and
HSS7 to HSS0 (subaddresses 06h and 07h; see
During horizontal blanking period between EAV and SAV the ITU-blanking code sequence
‘-80-10-80-10-...’ is transmitted.
The position of the F-bit is constant according to ITU-R BT 656 (see
Table
The V-bit can be generated in four different ways (see
OFTS1 and OFTS0 (subaddress 10h, bits 7 and 6), VRLN (subaddress 10h, bit 3) and
LCR2 to LCR24 (subaddresses 41h to 57h).
F and V bits change synchronously with the EAV code.
Bit
7
6
5
4
3 to 0
Section
Table
10).
Symbol
F
V
H
P[3:0]
SAV/EAV format
16).
9, subaddress 12h for details.
Description
logic 1
field bit
vertical blanking bit
H = 0 in SAV; H = 1 in EAV
reserved; evaluation not recommended (protection bits according to
ITU-R BT 656)
1st field: F = 0
2nd field: F = 1
for vertical timing see
VBI: V = 1
active video: V = 0
for vertical timing see
Rev. 02 — 9 May 2005
Table
28). If the YC-mode is selected, the VPO-bus
Table 9
Table 9
Figure
and
and
Table 9
Table 10
Table 10
24).
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
9-bit video input processor
and
Table
SAA7113H
Table 9
10) controlled via
and
Table
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20)