SSTUH32864EC/G NXP Semiconductors, SSTUH32864EC/G Datasheet - Page 6

• Manufacturer Part Number: SSTUH32864EC/G
• Manufacturer: NXP Semiconductors

Specifications of SSTUH32864EC/G

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -12mA
• Low Level Output Current: 12mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 450(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

Philips Semiconductors
Table 2:
[1]
[2]
[3]
9397 750 14137
Product data sheet
Symbol
GND
V
VREF
ZOH
ZOL
CK
CK
C0, C1
RESET
CSR, DCS
D1 to D25
DODT
DCKE
Q1 to Q25,
Q1A to Q14A,
Q1B to Q14B
QCS, QCSA,
QCSB
QODT, QODTA,
QODTB
QCKE, QCKEA,
QCKEB
n.c.
DNU
DD
Depends on configuration. See
Configurations:
Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0.
Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1.
Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1.
Configurations:
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0.
Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1.
Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = 1.
Pin description
5.2 Pin description
Pin
B3, B4, D3, D4,
F3, F4, H3, H4, K3,
K4, M3, M4, P3,
P4
A4, C3, C4, E3,
E4, G3, G4, J3, J4,
L3, L4, N3, N4, R3,
R4, T4
A3, T3
J5
J6
H1
J1
G6, G5
G2
J2, H2
A2, D2, G1
[1]
[1]
[1]
[1]
[1]
[1]
[1]
[1]
Figure
3,
Type
ground input
1.8 V nominal
0.9 V nominal
input
input
differential input
differential input
LVCMOS inputs
LVCMOS input
SSTL_18 input
SSTL_18 input
SSTL_18 input
SSTL_18 input
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
1.8 V CMOS
-
-
Figure
4, and
Rev. 01 — 22 April 2005
Figure 5
reserved for future use
reserved for future use
positive master clock input
negative master clock input
Chip select inputs (active LOW). Disables data outputs switching
Do-not-use. Ball internally connected to the die which should be
Description
ground
power supply voltage
input reference voltage
configuration control inputs
Asynchronous reset input (active LOW). Resets registers and
disables VREF data and clock differential-input receivers.
when both inputs are HIGH
Data inputs. Clocked in on the crossing of the rising edge of CK
and the falling edge of CK.
The outputs of this register will not be suspended by DCS and
CSR control.
The outputs of this register will not be suspended by DCS and
CSR control.
The outputs that are suspended by DCS and CSR control
data outputs that will not be suspended by DCS and CSR control
data outputs that will not be suspended by DCS and CSR control
data outputs that will not be suspended by DCS and CSR control
Not connected. Ball present but no internal connection to the die.
left open-circuit.
for ball number.
1.8 V high output drive DDR registered buffer
[2]
.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SSTUH32864
[3]
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