74SSTUA32866BFG8 IDT, Integrated Device Technology Inc, 74SSTUA32866BFG8 Datasheet - Page 12

• Manufacturer Part Number: 74SSTUA32866BFG8
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of 74SSTUA32866BFG8

• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Bits: 25
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 2.4ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Compliant

TIMING REQUIREMENTS OVER RECOMMENDED OPERATING FREE-AIR
TEMPERATURE RANGE
NOTES:
1. This parameter is not production tested.
2. Data and V
3. Data, V
SWITCHING CHARACTERISTICS OVER RECOMMENDED FREE-AIR OPERATING
RANGE (UNLESS OTHERWISE NOTED)
NOTES:
1. See TEST CIRCUITS AND WAVEFORMS.
2. Includes 350ps of test load transmission line delay.
3. This parameter is not production tested.
4. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate).
5. For reference only. Final values to be determined.
IDT74SSTUA32866
1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST
Symbol
t
INACT (1,3)
t
f
ACT (1,2)
CLOCK
t
dV/dt_Δ
t
Symbol
PDMSS
tw
SU
t
dV/dt_r
H
dV/dt_f
t
PDM
t
t
t
f
RPHL
RPHL
RPLH
t
t
MAX
t
PLH
PHL
PD
(2)
REF
(2,3)
(4)
, and clock inputs must be held at valid levels (not floating) a minimum time of t
REF
Parameter
Clock Frequency
Pulse Duration, CLK, CLK HIGH or LOW
Differential Inputs Active Time
Differential Inputs Inactive Time
Setup Time
Hold Time
inputs must be low a minimum time of t
Parameter
CLK and CLK to Q
CLK and CLK to Q (simultaneous switching)
RESET to Q
Output slew rate from 20% to 80%
Output slew rate from 20% to 80%
Output slew rate from 20% to 80%
CLK and CLK to PPO
CLK and CLK to QERR
CLK and CLK to QERR
RESET to PPO
RESET to QERR
DCS before CLK↑, CLK↓, CSR HIGH; CSR before CLK↑, CLK↓, DCS HIGH
DCS before CLK↑, CLK↓, CSR LOW
DODT, DCKE, and data before CLK↑, CLK↓
PAR_IN before CLK↑, CLK↓
DCS , DODT, DCKE, and data after CLK↑, CLK↓
PAR_IN after CLK↑, CLK↓
ACT
max, after RESET is taken HIGH.
12
(1)
0.5
1.2
Min
410
1.2
1
—
—
—
—
—
1
1
(5)
INACT
(5)
(5)
max, after RESET is taken LOW.
V
DD
= 1.8V ± 0.1V
Max.
1.8
2.4
1.9
3
—
2
3
4
4
1
3
3
(5)
(5)
(5)
COMMERCIAL TEMPERATURE RANGE
V
Min.
0.7
0.5
0.5
0.5
0.5
0.5
—
—
—
DD
1
= 1.8V ± 0.1V
MHz
V/ns
V/ns
V/ns
Unit
Max.
410
ns
ns
ns
ns
ns
ns
ns
ns
—
10
15
—
—
—
—
—
—
MHz
Unit
ns
ns
ns
ns
ns